1 files changed, 80 insertions, 0 deletions
diff --git a/rtl/src/verilog/novena_regs.v b/rtl/src/verilog/novena_regs.v
new file mode 100644
index 0000000..88b35ab
--- /dev/null
+++ b/rtl/src/verilog/novena_regs.v
@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+
+module novena_regs
+	(
+		input		wire  				clk,
+		input		wire					rst,
+
+		input		wire  				cs,
+		input		wire  				we,
+
+		input		wire 	[ 7 : 0]		address,
+		input		wire  [31 : 0]		write_data,
+		output	wire	[31 : 0]		read_data
+	);
+
+
+	//----------------------------------------------------------------
+	// Board-Level Registers
+	//----------------------------------------------------------------
+	localparam	ADDR_BOARD_TYPE		= 8'h00;		// board id
+	localparam	ADDR_FIRMWARE_VER		= 8'h01;		// bitstream version
+	localparam	ADDR_DUMMY_REG			= 8'hFF;		// general-purpose register
+
+
+	//----------------------------------------------------------------
+	// Constants
+	//----------------------------------------------------------------
+	localparam	NOVENA_BOARD_TYPE		= 32'h50565431;		// PVT1
+	localparam	NOVENA_DESIGN_VER		= 32'h00_01_00_0b;	// v0.1.0b
+
+
+		//
+		// Output Register
+		//
+	reg	[31: 0]	tmp_read_data;
+	assign read_data = tmp_read_data;
+	
+
+		/* This dummy register can be used by users to check that they can actually write something.
+		 */
+	 
+	reg	[31: 0]	reg_dummy;
+	
+	
+		//
+		// Access Handler
+		//
+	always @(posedge clk)
+		//
+		if (rst)	reg_dummy <= {32{1'b0}};
+		else if (cs) begin
+			//
+			if (we) begin
+				//
+				// WRITE handler
+				//
+				case (address)
+					ADDR_DUMMY_REG:	reg_dummy	<= write_data;
+				endcase
+				//
+			end else begin
+				//
+				// READ handler
+				//
+				case (address)
+					ADDR_BOARD_TYPE:		tmp_read_data	<= NOVENA_BOARD_TYPE;
+					ADDR_FIRMWARE_VER:	tmp_read_data	<= NOVENA_DESIGN_VER;
+					ADDR_DUMMY_REG:		tmp_read_data	<= reg_dummy;
+					//
+					default:					tmp_read_data	<= {32{1'b0}};	// read non-existent locations as zeroes
+					/*
+               default:					tmp_read_data	<= {32{1'bX}};	// don't care what to read from non-existent locations
+					*/
+				endcase
+				//
+			end
+			//
+		end
+
+endmodule