diff options
Diffstat (limited to 'rtl/src/ipcore')
| -rw-r--r-- | rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.gise | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.v | 17 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.veo | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.xco | 12 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.xise | 341 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm_flist.txt | 1 |
7 files changed, 351 insertions, 26 deletions
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs index 2ccce38..8fe7625 100644 --- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs +++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v" into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v" into library work</arg>
</msg>
</messages>
diff --git a/rtl/src/ipcore/clkmgr_dcm.gise b/rtl/src/ipcore/clkmgr_dcm.gise index ae9097a..ed6d0f7 100644 --- a/rtl/src/ipcore/clkmgr_dcm.gise +++ b/rtl/src/ipcore/clkmgr_dcm.gise @@ -19,7 +19,7 @@ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="../../../../src/ipcore/clkmgr_dcm.xise"/>
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clkmgr_dcm.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="clkmgr_dcm.asy" xil_pn:origination="imported"/>
diff --git a/rtl/src/ipcore/clkmgr_dcm.v b/rtl/src/ipcore/clkmgr_dcm.v index b719b86..71477a8 100644 --- a/rtl/src/ipcore/clkmgr_dcm.v +++ b/rtl/src/ipcore/clkmgr_dcm.v @@ -55,7 +55,7 @@ // "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -92,12 +92,11 @@ module clkmgr_dcm wire [7:0] status_int;
wire clkfb;
wire clk0;
- wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
- .CLKFX_DIVIDE (5),
- .CLKFX_MULTIPLY (8),
+ .CLKFX_DIVIDE (1),
+ .CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
@@ -116,7 +115,7 @@ module clkmgr_dcm .CLK270 (),
.CLK2X (),
.CLK2X180 (),
- .CLKFX (clkfx),
+ .CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
@@ -133,17 +132,15 @@ module clkmgr_dcm .DSSEN (1'b0));
assign INPUT_CLK_STOPPED = status_int[1];
- assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[2:1] == 2'b 0 ) );
+ assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) );
// Output buffering
//-----------------------------------
- BUFG clkf_buf
- (.O (clkfb),
- .I (clk0));
+ assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
- .I (clkfx));
+ .I (clk0));
diff --git a/rtl/src/ipcore/clkmgr_dcm.veo b/rtl/src/ipcore/clkmgr_dcm.veo index fa19d52..c4e1d31 100644 --- a/rtl/src/ipcore/clkmgr_dcm.veo +++ b/rtl/src/ipcore/clkmgr_dcm.veo @@ -54,7 +54,7 @@ // "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
diff --git a/rtl/src/ipcore/clkmgr_dcm.xco b/rtl/src/ipcore/clkmgr_dcm.xco index 06b89ec..37f1a1d 100644 --- a/rtl/src/ipcore/clkmgr_dcm.xco +++ b/rtl/src/ipcore/clkmgr_dcm.xco @@ -1,7 +1,7 @@ ##############################################################
#
# Xilinx Core Generator version 14.7
-# Date: Wed Jan 28 21:56:02 2015
+# Date: Sun Feb 01 07:49:40 2015
#
##############################################################
#
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0 CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.0
-CSET clkout1_requested_out_freq=80
+CSET clkout1_requested_out_freq=50
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.0
@@ -107,15 +107,15 @@ CSET component_name=clkmgr_dcm CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out1_port=CLK0
CSET dcm_clk_out2_port=CLK0
CSET dcm_clk_out3_port=CLK0
CSET dcm_clk_out4_port=CLK0
CSET dcm_clk_out5_port=CLK0
CSET dcm_clk_out6_port=CLK0
CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=5
-CSET dcm_clkfx_multiply=8
+CSET dcm_clkfx_divide=1
+CSET dcm_clkfx_multiply=4
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
@@ -266,4 +266,4 @@ CSET use_status=false MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
-# CRC: 9fa2003b
+# CRC: d6857c2d
diff --git a/rtl/src/ipcore/clkmgr_dcm.xise b/rtl/src/ipcore/clkmgr_dcm.xise index 6ab49ca..e6b0f8a 100644 --- a/rtl/src/ipcore/clkmgr_dcm.xise +++ b/rtl/src/ipcore/clkmgr_dcm.xise @@ -16,11 +16,11 @@ <files> <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF"> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> @@ -28,30 +28,359 @@ </files> <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> + <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> + <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> + <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> - <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> + <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> + <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> + <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> + <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> + <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> + <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> + <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> + <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> + <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Module|clkmgr_dcm" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="clkmgr_dcm.v" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clkmgr_dcm" xil_pn:valueState="non-default"/> + <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Include SIMPRIM Models in Verilog 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xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-01-29T01:56:27" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="35ECECEDE6BC496293C4671B28106B0F" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-01T08:50:04" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="67BEB73269CA45ADBC7997434CEC13CB" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> diff --git a/rtl/src/ipcore/clkmgr_dcm_flist.txt b/rtl/src/ipcore/clkmgr_dcm_flist.txt index 33943f8..bd1b2cd 100644 --- a/rtl/src/ipcore/clkmgr_dcm_flist.txt +++ b/rtl/src/ipcore/clkmgr_dcm_flist.txt @@ -2,7 +2,6 @@ _xmsgs\pn_parser.xmsgs
clkmgr_dcm.asy
clkmgr_dcm.gise
-clkmgr_dcm.sym
clkmgr_dcm.ucf
clkmgr_dcm.v
clkmgr_dcm.veo
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