diff options
Diffstat (limited to 'rtl/src/ipcore/_xmsgs')
| -rw-r--r-- | rtl/src/ipcore/_xmsgs/cg.xmsgs | 27 | ||||
| -rw-r--r-- | rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 15 |
2 files changed, 42 insertions, 0 deletions
diff --git a/rtl/src/ipcore/_xmsgs/cg.xmsgs b/rtl/src/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..985e6e3 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
+</msg>
+ +<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+ +<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+ +</messages> +
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..2ccce38 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v" into library work</arg>
+</msg>
+
+</messages>
+
|