diff options
Diffstat (limited to 'rtl/iseconfig/novena_baseline.xise')
| -rw-r--r-- | rtl/iseconfig/novena_baseline.xise | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/rtl/iseconfig/novena_baseline.xise b/rtl/iseconfig/novena_baseline.xise index a270ac9..a1b8766 100644 --- a/rtl/iseconfig/novena_baseline.xise +++ b/rtl/iseconfig/novena_baseline.xise @@ -15,56 +15,56 @@ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> <files> - <file xil_pn:name="src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> - <file xil_pn:name="src/verilog/novena_clkmgr.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/novena_clkmgr.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> - <file xil_pn:name="src/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> + <file xil_pn:name="../src/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> - <file xil_pn:name="src/verilog/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> - <file xil_pn:name="src/verilog/eim_arbiter.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/eim_arbiter.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> - <file xil_pn:name="src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> - <file xil_pn:name="src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> - <file xil_pn:name="src/verilog/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> - <file xil_pn:name="src/ucf/novena_baseline.ucf" xil_pn:type="FILE_UCF"> + <file xil_pn:name="../src/ucf/novena_baseline.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> - <file xil_pn:name="src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> - <file xil_pn:name="src/testbench/tb_demo_adder.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/testbench/tb_demo_adder.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="71"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="71"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="71"/> </file> - <file xil_pn:name="src/verilog/eim_indicator.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/eim_indicator.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> - <file xil_pn:name="src/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> + <file xil_pn:name="../src/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> </files> @@ -103,7 +103,7 @@ <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> @@ -194,7 +194,7 @@ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Module|novena_baseline_top" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top File" xil_pn:value="src/verilog/novena_baseline_top.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="../src/verilog/novena_baseline_top.v" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/novena_baseline_top" xil_pn:valueState="non-default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |