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-rw-r--r--rtl/build/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/rtl/build/Makefile b/rtl/build/Makefile
index cfac6ae..c51e783 100644
--- a/rtl/build/Makefile
+++ b/rtl/build/Makefile
@@ -5,6 +5,7 @@ part = xc6slx45csg324-3
top_module = novena_baseline_top
isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings64.sh
+ucf = ../src/ucf/novena_baseline.ucf
vfiles = \
../src/verilog/cdc_bus_pulse.v \