diff options
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 4d3a218..a18bfe6 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,28 +48,26 @@ module core_selector input wire [31 : 0] write_data ); -// parameter SHA256_BASE = 6'h14; -// wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); -// wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); - localparam SHA256_BASE_ADDR = 6'h14; wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; - wire read_access = sys_eim_wr & access_sha256; - wire write_access = sys_eim_rd & access_sha256; + wire read_access = sys_eim_rd & access_sha256; + wire write_access = sys_eim_wr & access_sha256; wire select = read_access | write_access; - sha256 sha256_inst( - .clk(sys_clk), - .reset_n(~sys_rst), - - .cs(select), - .we(write_access), + assign read_data = (sys_eim_rd) ? 32'hdeadbeef : 32'haa55aa55; - .address(sys_eim_addr[7 : 0]), - .write_data(write_data), - .read_data(read_data), - .error() - ); +// sha256 sha256_inst( +// .clk(sys_clk), +// .reset_n(~sys_rst), +// +// .cs(select), +// .we(write_access), +// +// .address(sys_eim_addr[7 : 0]), +// .write_data(write_data), +// .read_data(read_data), +// .error() +// ); endmodule |