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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-02-01 09:03:37 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-02-01 09:03:37 +0100 |
| commit | 5150947e0bfc393b03e49bcb37e1168eb02f5b67 (patch) | |
| tree | e800d87f2142c31fece7c15b1e26b368b670c624 /rtl/src/verilog/novena_baseline_top.v | |
| parent | 0d258b832847ca29bcf47f1904b7cc4a76e2a191 (diff) | |
Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.
Diffstat (limited to 'rtl/src/verilog/novena_baseline_top.v')
0 files changed, 0 insertions, 0 deletions