diff options
| author | Paul Selkirk <paul@psgd.org> | 2015-02-12 18:53:42 -0500 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-02-12 18:53:42 -0500 |
| commit | 8f0faf9fa1ece195eaf102191c571a32d7c1a232 (patch) | |
| tree | 7f690d0910da7dd24d841c83d96d1455bb3191f0 /rtl/src/verilog/eim_indicator.v | |
| parent | a758f34a103c9a58694f6bbe6b96a672e6881bef (diff) | |
| parent | f135907b11d6511cd260c4ab751a2bee2f30b662 (diff) | |
Merge branch 'coretest_hashes' of git.cryptech.is:test/novena_base into master
Diffstat (limited to 'rtl/src/verilog/eim_indicator.v')
| -rw-r--r-- | rtl/src/verilog/eim_indicator.v | 49 |
1 files changed, 21 insertions, 28 deletions
diff --git a/rtl/src/verilog/eim_indicator.v b/rtl/src/verilog/eim_indicator.v index 56c7190..cf9751d 100644 --- a/rtl/src/verilog/eim_indicator.v +++ b/rtl/src/verilog/eim_indicator.v @@ -6,7 +6,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -37,37 +37,30 @@ //====================================================================== module eim_indicator - ( - sys_clk, sys_rst, - eim_active, - led_out - ); + ( + input wire sys_clk, + input wire sys_rst, + input wire eim_active, + output wire led_out + ); - // - // Ports - // - input wire sys_clk; - input wire sys_rst; - input wire eim_active; - output wire led_out; + // + // Parameters + // + localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz. - // - // Parameters - // - localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz. + // + // Counter + // + reg [CNT_BITS-1:0] cnt; - // - // Counter - // - reg [CNT_BITS-1:0] cnt; + always @(posedge sys_clk) + // + if (sys_rst) cnt <= {CNT_BITS{1'b0}}; + else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1; + else if (eim_active) cnt <= {CNT_BITS{1'b1}}; - always @(posedge sys_clk) - // - if (sys_rst) cnt <= {CNT_BITS{1'b0}}; - else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1; - else if (eim_active) cnt <= {CNT_BITS{1'b1}}; - - assign led_out = ~cnt[CNT_BITS-1]; + assign led_out = ~cnt[CNT_BITS-1]; endmodule |