Updates from Pavel with new mux.

1. EIM arbiter was updated to take advantage of 3 additional address
lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address
lines instead of 16, that means 19-2=17 effective bits when using 32-bit
access.

2. In the doc directory there's a draft version of current EIM memory map.

3. I've figured out why you guys could not use read and write signals from
the arbiter the way they were supposed to be used. I was wrong when I
expected Joachim's cores to have registered outputs. They have a
combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so
we have to register data coming out of cores. I've added these three lines
to every core wrapper (sha1.v, sha256.v and sha512.v):
  reg [31 : 0]   tmp_read_data_reg;
  always @(posedge clk) tmp_read_data_reg <= tmp_read_data;
  assign read_data = tmp_read_data_reg;

4. Joachim told me, that we are going to have different types of cores
(HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have
separate modules for every core type. RNG and CIPHER selectors right now
are just templates with some dummy registers. Here is what was modified in
the HASH multiplexor:

4a. Core number 0 was added. It is not an actual HASH core, but a set of
global (board-level) registers. I've added three registers so far: board
type, bitstream version and one writeable dummy general-purpose register.

4b. Core instantiation was made conditional to allow selecting of what
cores to actually implement. We can have a project that offers a large
number of cores, so people can disable unnecessary cores to speed up
compile time and to save some slices for something else.

4c. I have disconnected .error() output from cores. As far as I understand
it gets asserted when some non-existent register is being addressed. In
most projects that I've seen writes to empty regions of memory are
discarded and reads return zeroes. If you really need this kind of error
checking, please re-connect this output as needed.

4d. core_selector.v has an instruction on how to add new HASH cores to our
design.

5. TC11() was added to hash_tester.c to check that we can read global
board-level registers and that we have access to segments other than
HASH. The last check reads dummy registers from RNG and CIPHER segments
(which are just templates now), this effectively tests the 3 new added
address bits.

1 files changed, 50 insertions, 0 deletions

diff --git a/rtl/iseconfig/.gitignore b/rtl/iseconfig/.gitignore
new file mode 100644
index 0000000..57a6191
--- /dev/null
+++ b/rtl/iseconfig/.gitignore
@@ -0,0 +1,50 @@
+_ngo/
+_xmsgs/
+fuse.xmsgs
+fuseRelaunch.cmd
+iseconfig/
+novena_baseline.gise
+novena_baseline_top.bgn
+novena_baseline_top.bit
+novena_baseline_top.bld
+novena_baseline_top.cmd_log
+novena_baseline_top.drc
+novena_baseline_top.lso
+novena_baseline_top.ncd
+novena_baseline_top.ngc
+novena_baseline_top.ngd
+novena_baseline_top.ngr
+novena_baseline_top.pad
+novena_baseline_top.par
+novena_baseline_top.pcf
+novena_baseline_top.prj
+novena_baseline_top.ptwx
+novena_baseline_top.stx
+novena_baseline_top.syr
+novena_baseline_top.twr
+novena_baseline_top.twx
+novena_baseline_top.unroutes
+novena_baseline_top.ut
+novena_baseline_top.xpi
+novena_baseline_top.xst
+novena_baseline_top_bitgen.xwbt
+novena_baseline_top_envsettings.html
+novena_baseline_top_map.map
+novena_baseline_top_map.mrp
+novena_baseline_top_map.ncd
+novena_baseline_top_map.ngm
+novena_baseline_top_map.xrpt
+novena_baseline_top_ngdbuild.xrpt
+novena_baseline_top_pad.csv
+novena_baseline_top_pad.txt
+novena_baseline_top_par.xrpt
+novena_baseline_top_summary.html
+novena_baseline_top_summary.xml
+novena_baseline_top_usage.xml
+novena_baseline_top_xst.xrpt
+par_usage_statistics.html
+usage_statistics_webtalk.html
+webtalk.log
+webtalk_pn.xml
+xlnx_auto_0_xdb/
+xst/