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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
clkmgr_dcm instance_name
(// Clock in ports
.CLK_IN1(CLK_IN1), // IN
// Clock out ports
.CLK_OUT1(CLK_OUT1), // OUT
// Status and control signals
.RESET(RESET),// IN
.INPUT_CLK_STOPPED(INPUT_CLK_STOPPED), // OUT
.CLK_VALID(CLK_VALID)); // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
