path: root/rtl/build/Makefile

project = novena_baseline_top
vendor = xilinx
family = spartan6
part = xc6slx45csg324-3
top_module = novena_baseline_top
isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings64.sh

vfiles = \
	../src/verilog/novena_baseline_top.v \
	../src/verilog/novena_clkmgr.v \
	../src/verilog/cdc_bus_pulse.v \
	../src/verilog/eim_arbiter.v \
	../src/verilog/demo_adder.v \
	../src/verilog/eim_da_phy.v \
	../src/verilog/eim_arbiter_cdc.v \
	../src/verilog/core_selector.v \
	../src/testbench/tb_demo_adder.v \
	../src/verilog/eim_indicator.v \
	../src/ipcore/clkmgr_dcm.v

include xilinx.mk