1 files changed, 37 insertions, 27 deletions

diff --git a/stm-fpgacfg.c b/stm-fpgacfg.c
index 6f6114d..54342bf 100644
--- a/stm-fpgacfg.c
+++ b/stm-fpgacfg.c
@@ -4,7 +4,7 @@
  * Functions for accessing the FPGA config memory and controlling
  * the low-level status of the FPGA (reset registers/reboot etc.).
  *
- * Copyright (c) 2016, NORDUnet A/S All rights reserved.
+ * Copyright (c) 2016-2017, NORDUnet A/S All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -33,20 +33,47 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "stm32f4xx_hal.h"
 #include "stm-fpgacfg.h"
 #include "stm-init.h"
 
-SPI_HandleTypeDef hspi_fpgacfg;
+static SPI_HandleTypeDef hspi_fpgacfg;
 
-struct spiflash_ctx fpgacfg_ctx = {&hspi_fpgacfg, PROM_CS_N_GPIO_Port, PROM_CS_N_Pin};
+static struct spiflash_ctx fpgacfg_ctx = {&hspi_fpgacfg, PROM_CS_N_GPIO_Port, PROM_CS_N_Pin};
 
-int fpgacfg_check_id()
+void fpgacfg_init(void)
+{
+    /* Give the FPGA access to it's bitstream ASAP (maybe this should actually
+     * be done in the application, before calling stm_init()).
+     */
+    fpgacfg_access_control(ALLOW_FPGA);
+
+    /* Set up GPIOs to manage access to the FPGA config memory.
+     * FPGACFG_GPIO_INIT is defined in stm-fpgacfg.h.
+     */
+    FPGACFG_GPIO_INIT();
+
+    /* SPI2 (FPGA config memory) init function */
+    hspi_fpgacfg.Instance = SPI2;
+    hspi_fpgacfg.Init.Mode = SPI_MODE_MASTER;
+    hspi_fpgacfg.Init.Direction = SPI_DIRECTION_2LINES;
+    hspi_fpgacfg.Init.DataSize = SPI_DATASIZE_8BIT;
+    hspi_fpgacfg.Init.CLKPolarity = SPI_POLARITY_LOW;
+    hspi_fpgacfg.Init.CLKPhase = SPI_PHASE_1EDGE;
+    hspi_fpgacfg.Init.NSS = SPI_NSS_SOFT;
+    hspi_fpgacfg.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+    hspi_fpgacfg.Init.FirstBit = SPI_FIRSTBIT_MSB;
+    hspi_fpgacfg.Init.TIMode = SPI_TIMODE_DISABLE;
+    hspi_fpgacfg.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+    hspi_fpgacfg.Init.CRCPolynomial = 10;
+    HAL_SPI_Init(&hspi_fpgacfg);
+}
+
+HAL_StatusTypeDef fpgacfg_check_id(void)
 {
     return n25q128_check_id(&fpgacfg_ctx);
 }
 
-int fpgacfg_write_data(uint32_t offset, const uint8_t *buf, const uint32_t len)
+HAL_StatusTypeDef fpgacfg_write_data(uint32_t offset, const uint8_t *buf, const uint32_t len)
 {
     return n25q128_write_data(&fpgacfg_ctx, offset, buf, len);
 }
@@ -86,29 +113,12 @@ void fpgacfg_reset_fpga(enum fpgacfg_reset reset)
     }
 }
 
-int fpgacfg_check_done(void)
+HAL_StatusTypeDef fpgacfg_check_done(void)
 {
-    GPIO_PinState status = HAL_GPIO_ReadPin(FPGA_DONE_Port, FPGA_DONE_Pin);
-    return (status == GPIO_PIN_SET);
+    return (HAL_GPIO_ReadPin(FPGA_DONE_Port, FPGA_DONE_Pin) == GPIO_PIN_SET) ? HAL_OK : HAL_ERROR;
 }
 
-int fpgacfg_erase_sectors(int num)
+HAL_StatusTypeDef fpgacfg_erase_sector(uint32_t sector_offset)
 {
-    if (num > N25Q128_NUM_SECTORS || num < 0) num = N25Q128_NUM_SECTORS;
-    while (num) {
-	int timeout = 200; /* times 10ms = 2 seconds timeout */
-	while (timeout--) {
-	    int i = n25q128_get_wip_flag(&fpgacfg_ctx);
-	    if (i < 0) return 0;
-	    if (! i) break;
-	    HAL_Delay(10);
-	}
-	if (! timeout) return 0;
-
-	if (! n25q128_erase_sector(&fpgacfg_ctx, num - 1)) {
-            return -1;
-        }
-	num--;
-    }
-    return 1;
+    return n25q128_erase_sector(&fpgacfg_ctx, sector_offset);
 }