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-rw-r--r--spiflash_n25q128.c412
1 files changed, 201 insertions, 211 deletions
diff --git a/spiflash_n25q128.c b/spiflash_n25q128.c
index 6e35a41..df53f19 100644
--- a/spiflash_n25q128.c
+++ b/spiflash_n25q128.c
@@ -6,7 +6,7 @@
* The Alpha board has two of these SPI flash memorys, the FPGA config memory
* and the keystore memory.
*
- * Copyright (c) 2016, NORDUnet A/S All rights reserved.
+ * Copyright (c) 2016-2017, NORDUnet A/S All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -35,320 +35,310 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "stm32f4xx_hal.h"
-#include "stm-fpgacfg.h"
-#include "stm-init.h"
+#include "spiflash_n25q128.h"
-#define _n25q128_select(ctx) HAL_GPIO_WritePin(ctx->cs_n_port, ctx->cs_n_pin, GPIO_PIN_RESET);
-#define _n25q128_deselect(ctx) HAL_GPIO_WritePin(ctx->cs_n_port, ctx->cs_n_pin, GPIO_PIN_SET);
+#define N25Q128_NUM_BYTES (N25Q128_PAGE_SIZE * N25Q128_NUM_PAGES)
+#if N25Q128_SECTOR_SIZE * N25Q128_NUM_SECTORS != N25Q128_NUM_BYTES || \
+ N25Q128_SUBSECTOR_SIZE * N25Q128_NUM_SUBSECTORS != N25Q128_NUM_BYTES
+#error Inconsistent definitions for pages / sectors / subsectors
+#endif
-int _n25q128_get_wel_flag(struct spiflash_ctx *ctx);
+static inline void _n25q128_select(struct spiflash_ctx *ctx)
+{
+ HAL_GPIO_WritePin(ctx->cs_n_port, ctx->cs_n_pin, GPIO_PIN_RESET);
+}
+
+static inline void _n25q128_deselect(struct spiflash_ctx *ctx)
+{
+ HAL_GPIO_WritePin(ctx->cs_n_port, ctx->cs_n_pin, GPIO_PIN_SET);
+}
-int n25q128_check_id(struct spiflash_ctx *ctx)
+/* Read a bit from the status register. */
+static inline int _n25q128_get_status_bit(struct spiflash_ctx *ctx, unsigned bitnum)
{
// tx, rx buffers
- uint8_t spi_tx[4];
- uint8_t spi_rx[4];
+ uint8_t spi_tx[2];
+ uint8_t spi_rx[2];
- // result
- HAL_StatusTypeDef ok;
+ //assert(bitnum < sizeof(uint8_t));
- // send READ ID command
- spi_tx[0] = N25Q128_COMMAND_READ_ID;
+ // send READ STATUS command
+ spi_tx[0] = N25Q128_COMMAND_READ_STATUS;
- // select, send command & read response, deselect
+ // send command, read response, deselect
_n25q128_select(ctx);
- ok = HAL_SPI_TransmitReceive(ctx->hspi, spi_tx, spi_rx, 4, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
+ int ok =
+ HAL_SPI_TransmitReceive(ctx->hspi, spi_tx, spi_rx, 2, N25Q128_SPI_TIMEOUT) == HAL_OK;
_n25q128_deselect(ctx);
// check
- if (ok != HAL_OK) return 0;
-
- // parse response (note, that the very first byte was received during the
- // transfer of the command byte, so it contains garbage and should
- // be ignored here)
- if (spi_rx[1] != N25Q128_ID_MANUFACTURER) return 0;
- if (spi_rx[2] != N25Q128_ID_DEVICE_TYPE) return 0;
- if (spi_rx[3] != N25Q128_ID_DEVICE_CAPACITY) return 0;
+ if (!ok) return -1;
// done
- return 1;
+ return ((spi_rx[1] >> bitnum) & 1);
}
-
-int n25q128_read_page(struct spiflash_ctx *ctx, uint32_t page_offset, uint8_t *page_buffer)
+/* Read the Write Enable Latch bit in the status register. */
+static inline int _n25q128_get_wel_flag(struct spiflash_ctx *ctx)
{
- // tx buffer
- uint8_t spi_tx[4];
-
- // result
- HAL_StatusTypeDef ok;
-
- // check offset
- if (page_offset >= N25Q128_NUM_PAGES) return 0;
-
- // calculate byte address
- page_offset *= N25Q128_PAGE_SIZE;
-
- // prepare READ command
- spi_tx[0] = N25Q128_COMMAND_READ_PAGE;
- spi_tx[1] = (uint8_t)(page_offset >> 16);
- spi_tx[2] = (uint8_t)(page_offset >> 8);
- spi_tx[3] = (uint8_t)(page_offset >> 0);
-
- // activate, send command
- _n25q128_select(ctx);
- ok = HAL_SPI_Transmit(ctx->hspi, spi_tx, 4, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
-
- // check
- if (ok != HAL_OK) {
- _n25q128_deselect(ctx);
- return 0;
- }
-
- // read response, deselect
- ok = HAL_SPI_Receive(ctx->hspi, page_buffer, N25Q128_PAGE_SIZE, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
- _n25q128_deselect(ctx);
-
- // check
- if (ok != HAL_OK) return 0;
+ return _n25q128_get_status_bit(ctx, 1);
+}
- // done
- return 1;
+/* Read the Write In Progress bit in the status register. */
+static inline int _n25q128_get_wip_flag(struct spiflash_ctx *ctx)
+{
+ return _n25q128_get_status_bit(ctx, 0);
}
+/* Wait until the flash memory is done writing */
+static HAL_StatusTypeDef _n25q128_wait_while_wip(struct spiflash_ctx *ctx, uint32_t timeout)
+{
+ uint32_t tick_end = HAL_GetTick() + timeout;
+
+ do {
+ switch (_n25q128_get_wip_flag(ctx)) {
+ case 0:
+ return HAL_OK;
+ case -1:
+ return HAL_ERROR;
+ default:
+ /* try again */
+ continue;
+ }
+ } while (HAL_GetTick() < tick_end);
+
+ return HAL_TIMEOUT;
+}
-int n25q128_write_page(struct spiflash_ctx *ctx, uint32_t page_offset, const uint8_t *page_buffer)
+/* Send the Write Enable command */
+static HAL_StatusTypeDef _n25q128_write_enable(struct spiflash_ctx *ctx)
{
// tx buffer
- uint8_t spi_tx[4];
-
- // result
- HAL_StatusTypeDef ok;
-
- // check offset
- if (page_offset >= N25Q128_NUM_PAGES) return 0;
+ uint8_t spi_tx[1];
// enable writing
spi_tx[0] = N25Q128_COMMAND_WRITE_ENABLE;
// activate, send command, deselect
_n25q128_select(ctx);
- ok = HAL_SPI_Transmit(ctx->hspi, spi_tx, 1, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
+ int ok =
+ HAL_SPI_Transmit(ctx->hspi, spi_tx, 1, N25Q128_SPI_TIMEOUT) == HAL_OK;
_n25q128_deselect(ctx);
// check
- if (ok != HAL_OK) return 0;
+ if (!ok) return HAL_ERROR;
// make sure, that write enable did the job
- int wel = _n25q128_get_wel_flag(ctx);
- if (wel != 1) return 0;
+ return _n25q128_get_wel_flag(ctx) ? HAL_OK : HAL_ERROR;
+}
- // calculate byte address
- page_offset *= N25Q128_PAGE_SIZE;
+HAL_StatusTypeDef n25q128_check_id(struct spiflash_ctx *ctx)
+{
+ // tx, rx buffers
+ uint8_t spi_tx[4];
+ uint8_t spi_rx[4];
- // prepare PROGRAM PAGE command
- spi_tx[0] = N25Q128_COMMAND_PAGE_PROGRAM;
- spi_tx[1] = (uint8_t)(page_offset >> 16);
- spi_tx[2] = (uint8_t)(page_offset >> 8);
- spi_tx[3] = (uint8_t)(page_offset >> 0);
+ // send READ ID command
+ spi_tx[0] = N25Q128_COMMAND_READ_ID;
- // activate, send command
+ // select, send command & read response, deselect
_n25q128_select(ctx);
- ok = HAL_SPI_Transmit(ctx->hspi, spi_tx, 4, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
-
- // check
- if (ok != HAL_OK) {
- _n25q128_deselect(ctx);
- return 0;
- }
-
- // send data, deselect
- ok = HAL_SPI_Transmit(ctx->hspi, (uint8_t *) page_buffer, N25Q128_PAGE_SIZE, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
+ int ok =
+ HAL_SPI_TransmitReceive(ctx->hspi, spi_tx, spi_rx, 4, N25Q128_SPI_TIMEOUT) == HAL_OK;
_n25q128_deselect(ctx);
// check
- if (ok != HAL_OK) return 0;
+ if (!ok) return HAL_ERROR;
- // done
- return 1;
+ // parse response (note, that the very first byte was received during the
+ // transfer of the command byte, so it contains garbage and should
+ // be ignored here)
+ return
+ (spi_rx[1] == N25Q128_ID_MANUFACTURER &&
+ spi_rx[2] == N25Q128_ID_DEVICE_TYPE &&
+ spi_rx[3] == N25Q128_ID_DEVICE_CAPACITY) ? HAL_OK : HAL_ERROR;
}
-int n25q128_get_wip_flag(struct spiflash_ctx *ctx)
+HAL_StatusTypeDef n25q128_write_page(struct spiflash_ctx *ctx, uint32_t page_offset, const uint8_t *page_buffer)
{
- // tx, rx buffers
- uint8_t spi_tx[2];
- uint8_t spi_rx[2];
+ // tx buffer
+ uint8_t spi_tx[4];
- // result
- HAL_StatusTypeDef ok;
+ // check offset
+ if (page_offset >= N25Q128_NUM_PAGES) return HAL_ERROR;
- // send READ STATUS command
- spi_tx[0] = N25Q128_COMMAND_READ_STATUS;
+ // enable writing
+ if (_n25q128_write_enable(ctx) != 0) return HAL_ERROR;
- // send command, read response, deselect
+ // calculate byte address
+ uint32_t byte_offset = page_offset * N25Q128_PAGE_SIZE;
+
+ // prepare PROGRAM PAGE command
+ spi_tx[0] = N25Q128_COMMAND_PAGE_PROGRAM;
+ spi_tx[1] = (uint8_t)(byte_offset >> 16);
+ spi_tx[2] = (uint8_t)(byte_offset >> 8);
+ spi_tx[3] = (uint8_t)(byte_offset >> 0);
+
+ // activate, send command, send data, deselect
_n25q128_select(ctx);
- ok = HAL_SPI_TransmitReceive(ctx->hspi, spi_tx, spi_rx, 2, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
+ int ok =
+ HAL_SPI_Transmit(ctx->hspi, spi_tx, 4, N25Q128_SPI_TIMEOUT) == HAL_OK &&
+ HAL_SPI_Transmit(ctx->hspi, (uint8_t *) page_buffer, N25Q128_PAGE_SIZE, N25Q128_SPI_TIMEOUT) == HAL_OK;
_n25q128_deselect(ctx);
// check
- if (ok != HAL_OK) return -1;
+ if (!ok) return HAL_ERROR;
- // done
- return (spi_rx[1] & 1);
+ // wait until write finishes
+ return _n25q128_wait_while_wip(ctx, 1000);
}
-int n25q128_erase_sector(struct spiflash_ctx *ctx, uint32_t sector_offset)
+static HAL_StatusTypeDef n25q128_erase_something(struct spiflash_ctx *ctx, uint8_t command, uint32_t byte_offset)
{
+ // check offset
+ if (byte_offset >= N25Q128_NUM_BYTES) return HAL_ERROR;
+
// tx buffer
uint8_t spi_tx[4];
- // result
- HAL_StatusTypeDef ok;
-
- // check offset
- if (sector_offset >= N25Q128_NUM_SECTORS) return 0;
-
// enable writing
- spi_tx[0] = N25Q128_COMMAND_WRITE_ENABLE;
+ if (_n25q128_write_enable(ctx) != 0) return HAL_ERROR;
- // select, send command, deselect
+ // send command (ERASE SECTOR or ERASE SUBSECTOR)
+ spi_tx[0] = command;
+ spi_tx[1] = (uint8_t)(byte_offset >> 16);
+ spi_tx[2] = (uint8_t)(byte_offset >> 8);
+ spi_tx[3] = (uint8_t)(byte_offset >> 0);
+
+ // activate, send command, deselect
_n25q128_select(ctx);
- ok = HAL_SPI_Transmit(ctx->hspi, spi_tx, 1, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
+ int ok =
+ HAL_SPI_Transmit(ctx->hspi, spi_tx, 4, N25Q128_SPI_TIMEOUT) == HAL_OK;
_n25q128_deselect(ctx);
// check
- if (ok != HAL_OK) return 0;
+ if (!ok) return HAL_ERROR;
- // make sure, that write enable did the job
- int wel = _n25q128_get_wel_flag(ctx);
- if (wel != 1) return 0;
-
- // calculate byte address
- sector_offset *= N25Q128_SECTOR_SIZE;
+ // wait for erase to finish
+ return _n25q128_wait_while_wip(ctx, 1000);
+}
- // send ERASE SUBSECTOR command
- spi_tx[0] = N25Q128_COMMAND_ERASE_SECTOR;
- spi_tx[1] = (uint8_t)(sector_offset >> 16);
- spi_tx[2] = (uint8_t)(sector_offset >> 8);
- spi_tx[3] = (uint8_t)(sector_offset >> 0);
- // activate, send command, deselect
- _n25q128_select(ctx);
- ok = HAL_SPI_Transmit(ctx->hspi, spi_tx, 4, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
- _n25q128_deselect(ctx);
+HAL_StatusTypeDef n25q128_erase_sector(struct spiflash_ctx *ctx, uint32_t sector_offset)
+{
+ return n25q128_erase_something(ctx, N25Q128_COMMAND_ERASE_SECTOR,
+ sector_offset * N25Q128_SECTOR_SIZE);
+}
- // check
- if (ok != HAL_OK) return 0;
- // done
- return 1;
+HAL_StatusTypeDef n25q128_erase_subsector(struct spiflash_ctx *ctx, uint32_t subsector_offset)
+{
+ return n25q128_erase_something(ctx, N25Q128_COMMAND_ERASE_SUBSECTOR,
+ subsector_offset * N25Q128_SUBSECTOR_SIZE);
}
-int _n25q128_get_wel_flag(struct spiflash_ctx *ctx)
+HAL_StatusTypeDef n25q128_erase_bulk(struct spiflash_ctx *ctx)
{
- // tx, rx buffers
- uint8_t spi_tx[2];
- uint8_t spi_rx[2];
+ // tx buffer
+ uint8_t spi_tx[1];
- // result
- HAL_StatusTypeDef ok;
+ // enable writing
+ if (_n25q128_write_enable(ctx) != 0) return HAL_ERROR;
- // send READ STATUS command
- spi_tx[0] = N25Q128_COMMAND_READ_STATUS;
+ // send command
+ spi_tx[0] = N25Q128_COMMAND_ERASE_BULK;
- // send command, read response, deselect
+ // activate, send command, deselect
_n25q128_select(ctx);
- ok = HAL_SPI_TransmitReceive(ctx->hspi, spi_tx, spi_rx, 2, N25Q128_SPI_TIMEOUT);
- HAL_Delay(1);
+ int ok =
+ HAL_SPI_Transmit(ctx->hspi, spi_tx, 1, N25Q128_SPI_TIMEOUT) == HAL_OK;
_n25q128_deselect(ctx);
// check
- if (ok != HAL_OK) return -1;
+ if (!ok) return HAL_ERROR;
- // done
- return ((spi_rx[1] >> 1) & 1);
+ // wait for erase to finish
+ return _n25q128_wait_while_wip(ctx, 60000);
}
-/* Wait until the flash memory is done writing (wip = Write In Progress) */
-inline int _wait_while_wip(struct spiflash_ctx *ctx, uint32_t timeout)
-{
- int i;
- while (timeout--) {
- i = n25q128_get_wip_flag(ctx);
- if (i < 0) return 0;
- if (! i) break;
- HAL_Delay(10);
- }
- return 1;
-}
-/* This function performs erasure if needed, and then writing of a number of pages to the flash memory */
-int n25q128_write_data(struct spiflash_ctx *ctx, uint32_t offset, const uint8_t *buf, const uint32_t len)
+/* This function writes of a number of pages to the flash memory.
+ * The caller is responsible for ensuring that the pages have been erased.
+ */
+HAL_StatusTypeDef n25q128_write_data(struct spiflash_ctx *ctx, uint32_t offset, const uint8_t *buf, const uint32_t len)
{
uint32_t page;
- /* Ensure alignment */
- if ((offset % N25Q128_PAGE_SIZE) != 0) return -1;
- if ((len % N25Q128_PAGE_SIZE) != 0) return -2;
-
- if ((offset % N25Q128_SECTOR_SIZE) == 0) {
- /* first page in sector, need to erase sector */
-
- if (! _wait_while_wip(ctx, 1000)) return -3;
-
- if (! n25q128_erase_sector(ctx, offset / N25Q128_SECTOR_SIZE)) {
- return -4;
- }
- }
+ /*
+ * The data sheet says:
+ * If the bits of the least significant address, which is the starting
+ * address, are not all zero, all data transmitted beyond the end of the
+ * current page is programmed from the starting address of the same page.
+ * If the number of bytes sent to the device exceed the maximum page size,
+ * previously latched data is discarded and only the last maximum
+ * page-size number of data bytes are guaranteed to be programmed
+ * correctly within the same page. If the number of bytes sent to the
+ * device is less than the maximum page size, they are correctly
+ * programmed at the specified addresses without any effect on the other
+ * bytes of the same page.
+ *
+ * This is sufficiently confusing that it makes sense to constrain the API
+ * to page alignment in address and length, because that's how we're using
+ * it anyway.
+ */
+
+ if (offset % N25Q128_PAGE_SIZE != 0 || len % N25Q128_PAGE_SIZE != 0) return HAL_ERROR;
for (page = 0; page < len / N25Q128_PAGE_SIZE; page++) {
- if (! _wait_while_wip(ctx, 1000)) return -5;
-
- if (! n25q128_write_page(ctx, offset / N25Q128_PAGE_SIZE, buf)) {
- return -6;
+ if (n25q128_write_page(ctx, offset / N25Q128_PAGE_SIZE, buf) != 0) {
+ return HAL_ERROR;
}
buf += N25Q128_PAGE_SIZE;
offset += N25Q128_PAGE_SIZE;
-
- /* XXX read back data and verify it, or maybe just verify ability to write
- * to memory by verifying the contents of one page after erase?
- */
}
- return 1;
+ return HAL_OK;
}
/* This function reads zero or more pages from the SPI flash. */
-int n25q128_read_data(struct spiflash_ctx *ctx, uint32_t offset, uint8_t *buf, const uint32_t len)
+HAL_StatusTypeDef n25q128_read_data(struct spiflash_ctx *ctx, uint32_t offset, uint8_t *buf, const uint32_t len)
{
- uint32_t page;
+ // tx buffer
+ uint8_t spi_tx[4];
- /* Ensure alignment */
- if ((offset % N25Q128_PAGE_SIZE) != 0) return -1;
- if ((len % N25Q128_PAGE_SIZE) != 0) return -2;
+ /*
+ * The data sheet says:
+ * The addressed byte can be at any location, and the address
+ * automatically increments to the next address after each byte of data is
+ * shifted out; therefore, the entire memory can be read with a single
+ * command. The operation is terminated by driving S# [chip select] HIGH
+ * at any time during data output.
+ *
+ * We're only going to call this with page-aligned address and length, but
+ * we're not going to enforce it here.
+ */
+
+ // avoid overflow
+ if (offset + len > N25Q128_NUM_BYTES) return HAL_ERROR;
- for (page = 0; page < len / N25Q128_PAGE_SIZE; page++) {
- if (! n25q128_read_page(ctx, offset / N25Q128_PAGE_SIZE, buf)) {
- return -3;
- }
- buf += N25Q128_PAGE_SIZE;
- offset += N25Q128_PAGE_SIZE;
- }
+ // prepare READ command
+ spi_tx[0] = N25Q128_COMMAND_READ;
+ spi_tx[1] = (uint8_t)(offset >> 16);
+ spi_tx[2] = (uint8_t)(offset >> 8);
+ spi_tx[3] = (uint8_t)(offset >> 0);
- return 1;
+ // activate, send command, read response, deselect
+ _n25q128_select(ctx);
+ int ok =
+ HAL_SPI_Transmit(ctx->hspi, spi_tx, 4, N25Q128_SPI_TIMEOUT) == HAL_OK &&
+ HAL_SPI_Receive(ctx->hspi, buf, len, N25Q128_SPI_TIMEOUT) == HAL_OK;
+ _n25q128_deselect(ctx);
+
+ // check
+ return ok ? HAL_OK : HAL_ERROR;
}
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