Add FPGA bitstream upload command to cli-test.

This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:

filetransfer --fpga /path/to/bitstream

The bitstream is identified by 'file' e.g. like this:

alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164

1 files changed, 9 insertions, 3 deletions

diff --git a/stm-init.c b/stm-init.c
index 4421b21..9b86a30 100644
--- a/stm-init.c
+++ b/stm-init.c
@@ -81,6 +81,12 @@ void stm_init(void)
   /* Initialize all configured peripherals */
 #ifdef HAL_GPIO_MODULE_ENABLED
   MX_GPIO_Init();
+  #ifdef HAL_SPI_MODULE_ENABLED
+  /* Give the FPGA access to it's bitstream ASAP (maybe this should actually
+   * be done in the application, before calling stm_init()).
+   */
+  fpgacfg_give_access_to_fpga();
+  #endif
 #endif
 #ifdef HAL_UART_MODULE_ENABLED
   MX_USART1_UART_Init();
@@ -161,9 +167,9 @@ static void MX_GPIO_Init(void)
   /* Set up GPIOs to manage access to the FPGA config memory. */
 
   /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOI_CLK_ENABLE();
-  __HAL_RCC_GPIOF_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __GPIOI_CLK_ENABLE();
+  __GPIOF_CLK_ENABLE();
+  __GPIOB_CLK_ENABLE();
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(PROM_FPGA_DIS_GPIO_Port, PROM_FPGA_DIS_Pin, GPIO_PIN_RESET);