Add FPGA bitstream upload command to cli-test.

This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:

filetransfer --fpga /path/to/bitstream

The bitstream is identified by 'file' e.g. like this:

alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164

1 files changed, 17 insertions, 0 deletions

diff --git a/stm-fpgacfg.c b/stm-fpgacfg.c
index 0026b9e..0d255e5 100644
--- a/stm-fpgacfg.c
+++ b/stm-fpgacfg.c
@@ -34,6 +34,7 @@
 
 #include "stm32f4xx_hal.h"
 #include "stm-fpgacfg.h"
+#include "stm-init.h"
 
 SPI_HandleTypeDef hspi_fpgacfg;
 
@@ -277,3 +278,19 @@ int _n25q128_get_wel_flag(void)
     // done
     return ((spi_rx[1] >> 1) & 1);
 }
+
+void fpgacfg_give_access_to_stm32()
+{
+    // fpga disable = 1
+    HAL_GPIO_WritePin(GPIOI, GPIO_PIN_14, GPIO_PIN_SET);
+    // arm enable = 0
+    HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_RESET);
+}
+
+void fpgacfg_give_access_to_fpga()
+{
+    // fpga disable = 0
+    HAL_GPIO_WritePin(GPIOI, GPIO_PIN_14, GPIO_PIN_RESET);
+    // arm enable = 1
+    HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_SET);
+}