Add FPGA bitstream upload command to cli-test.

This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:

filetransfer --fpga /path/to/bitstream

The bitstream is identified by 'file' e.g. like this:

alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164

0 files changed, 0 insertions, 0 deletions