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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2021-09-13 11:45:09 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2021-09-13 11:45:09 +0300
commit71f6c636d73e218baa2c5f8dc5057f54029132ea (patch)
treef6aa5fe4f15b63393625a8d316282c5fe4b99a76 /libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4
parentb8e9996f96f1de95ff2c09fb35a839a7783d3fca (diff)
Initialize I/O pins of SPI3, which is used to configure iCE40-based MKM.
Note, that SPI3 is alternate function 6, unlike SPI1 & SPI2 which are both AF5.
Diffstat (limited to 'libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4')
-rw-r--r--libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c
index f64e6ce..6983c70 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c
@@ -295,6 +295,24 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
/* Peripheral clock enable */
__SPI2_CLK_ENABLE();
+ } else if (hspi->Instance == SPI3) {
+ /* SPI3 is the iCE40 MKM slave config interface
+ *
+ * SPI3 GPIO Configuration
+ * PC10 ------> SPI3_SCK
+ * PC11 ------> SPI3_MISO
+ * PC12 ------> SPI3_MOSI
+ */
+ __GPIOC_CLK_ENABLE();
+ GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /* Peripheral clock enable */
+ __SPI3_CLK_ENABLE();
}
}