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AgeCommit message (Expand)Author
2018-12-07Adding untested code to implement timer controlled automatic zeroisation of k...Joachim Strömbergson
2018-12-07Adding API support for key loaded status and key timeout control. Added ports...Joachim Strömbergson
2018-09-04Updated rtl and tb to support parameterized memory size.Joachim Strömbergson
2018-08-24We probably want to be able to read data too.Joachim Strömbergson
2018-08-24Killed the bank switching.Joachim Strömbergson
2018-08-24Performed Verilog parameter magic to make the design scaleable in terms of ca...Joachim Strömbergson
2018-08-23Adding top level defines for setting size and address bits.Joachim Strömbergson
2018-08-16Adding delay cycle to API regs to match the latency for accessing the blockRA...Joachim Strömbergson
2018-07-24Added explicit width specification for constant to silence truncation warning.Joachim Strömbergson
2018-07-06(1) Updated version to reflect status. (2) Minor fix after running sim in Mod...Joachim Strömbergson
2018-07-06Debugged key unwrap. First testcase for unwerap passed. Added some more debug...Joachim Strömbergson
2018-07-06(1) Fixed dump of core_addr in testbench to actually show the core_addr. Fixe...Joachim Strömbergson
2018-07-05Adding wait state to allow access from memory to complete. Should be possible...Joachim Strömbergson
2018-07-05Fixing block counter init bug. Enabling detailed debugging. Fixing minor nits.Joachim Strömbergson
2018-07-05Updated keywrap logic to support unwrap. Split state to handle next start in ...Joachim Strömbergson
2018-07-05Adding state and counter functionality to support unwrap. Changed name of def...Joachim Strömbergson
2018-07-05Removed a few states and a few cycles.Joachim Strömbergson
2018-07-05We haz keywrap! Time to add more testcases and make them self testing. Oh and...Joachim Strömbergson
2018-07-05Debugged keywrap processing including A update. All AES operations works corr...Joachim Strömbergson
2018-07-05Fixed memory word order. Fixed a number of bugs. First block encrypted correc...Joachim Strömbergson
2018-07-05Removed the streaming interface in favor of a normal address based interface....Joachim Strömbergson
2018-07-03Good news: The core peformcs all AES operations and stops after correct numbe...Joachim Strömbergson
2018-07-03Debugged a lot of minor errors and added a lot of debug functions. Things are...Joachim Strömbergson
2018-06-29Fixed nits found during linting.Joachim Strömbergson
2018-06-29Fixed bugs in the API decoding logic.Joachim Strömbergson
2018-06-29Completed first version of core that should have all functionality needed to ...Joachim Strömbergson
2018-06-29Changed name in API for A words to clarify their meaning. Corrected case orde...Joachim Strömbergson
2018-06-28Adding a lot of functionality. Starting to get everthing in place.Joachim Strömbergson
2018-06-28A lot of cleanup of interconnections between cores and hierarchy. Fixed a num...Joachim Strömbergson
2018-06-28Interface debugging.Joachim Strömbergson
2018-06-28Updated top level wrapper to better match the planned API. Updated core inter...Joachim Strömbergson
2018-06-27Adding initial version of top level wrapper for the keywrap core.Joachim Strömbergson
2018-06-26Adding more functionality in the core. Updated Makefile to build and simulate...Joachim Strömbergson
2018-06-22(1) Added initial version of keywrap_core which will implement the actual wra...Joachim Strömbergson
2018-06-21Increased size of memory to 64 kByte to match what is needed for key wrap. No...Joachim Strömbergson
2018-06-21Reworked code a bit to match what ISE expects to map to block RAM instances.Joachim Strömbergson
2018-06-21Implemented test design for key wrap memory. To be tested in ISE.Joachim Strömbergson
2018-06-19Adding initial version of repo and design for core implementing aes key wrap.Joachim Strömbergson
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