aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/rtl/keywrap.v12
-rw-r--r--src/rtl/keywrap_core.v65
-rw-r--r--src/tb/tb_keywrap_core.v36
3 files changed, 92 insertions, 21 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 829ddd1..cc6f8ac 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -152,6 +152,9 @@ module keywrap #(parameter ADDR_BITS = 13)
reg [31 : 0] key_reg [0 : 7];
reg key_we;
+ reg [31 : 0] mstatus_reg;
+ reg mstatus_we;
+
reg [31 : 0] api_rd_delay_reg;
reg [31 : 0] api_rd_delay_new;
@@ -218,6 +221,7 @@ module keywrap #(parameter ADDR_BITS = 13)
.key(core_key),
.keylen(keylen_reg),
+ .status(mstatus_reg),
.mkey(core_mkey),
.mstatus(core_mstatus),
@@ -250,6 +254,7 @@ module keywrap #(parameter ADDR_BITS = 13)
mkey_mstatus_reg <= 1'h0;
encdec_reg <= 1'h0;
keylen_reg <= 1'h0;
+ mstatus_reg <= 32'h0;
rlen_reg <= {RLEN_BITS{1'h0}};
valid_reg <= 1'h0;
ready_reg <= 1'h0;
@@ -284,6 +289,9 @@ module keywrap #(parameter ADDR_BITS = 13)
if (a1_we)
a1_reg <= write_data;
+ if (mstatus_we)
+ mstatus_reg <= write_data;
+
if (key_we)
key_reg[address[2 : 0]] <= write_data;
end
@@ -307,6 +315,7 @@ module keywrap #(parameter ADDR_BITS = 13)
core_api_we = 1'h0;
a0_we = 1'h0;
a1_we = 1'h0;
+ mstatus_we = 1'h0;
tmp_read_data = 32'h0;
tmp_error = 1'h0;
api_rd_delay_new = 32'h0;
@@ -342,6 +351,9 @@ module keywrap #(parameter ADDR_BITS = 13)
if (address == {{PAD{1'h0}}, ADDR_A1})
a1_we = 1'h1;
+ if (address == {{PAD{1'h0}}, ADDR_MSTATUS})
+ mstatus_we = 1'h1;
+
if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) &&
(address <= {{PAD{1'h0}}, ADDR_KEY7}))
key_we = 1'h1;
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 8688e31..00e8391 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -61,9 +61,9 @@ module keywrap_core #(parameter MEM_BITS = 11)
output wire valid,
input wire [(MEM_BITS - 2) : 0] rlen,
-
input wire [255 : 0] key,
input wire keylen,
+ input wire [31 : 0] status,
output wire [255 : 0] mkey,
output wire [31 : 0] mstatus,
@@ -95,9 +95,13 @@ module keywrap_core #(parameter MEM_BITS = 11)
localparam CTRL_NEXT_FINALIZE = 6'ha;
localparam CTRL_MKM_RD_START = 6'h10;
- localparam CTRL_MKM_RD_END = 6'h11;
+ localparam CTRL_MKM_RD_WAIT0 = 6'h11;
+ localparam CTRL_MKM_RD_STATUS = 6'h12;
+ localparam CTRL_MKM_RD_END = 6'h13;
+
localparam CTRL_MKM_WR_START = 6'h18;
- localparam CTRL_MKM_WR_END = 6'h19;
+ localparam CTRL_MKM_WR_WAIT0 = 6'h19;
+ localparam CTRL_MKM_WR_END = 6'h1a;
// API for mkm used by the core.
localparam MKM_ADDR_CTRL = 8'h08;
@@ -111,8 +115,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
localparam MKM_ADDR_EMEM_DATA = 8'h20;
// Addresses for storage in the mkm
- localparam MKM_STATUS_WORD = 8'h00;
- localparam MKM_KEY_BASE_WORD = 8'h04;
+ localparam MKM_STATUS_WORD = 16'h00;
+ localparam MKM_KEY_BASE_WORD = 16'h04;
localparam DEFAULT_SCLK_DIV = 16'h0020;
@@ -264,7 +268,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
assign a_result = a_reg;
assign ready = ready_reg;
assign valid = valid_reg;
- assign mkm_status = mkm_status_reg;
+ assign mstatus = mkm_status_reg;
//----------------------------------------------------------------
@@ -637,11 +641,45 @@ module keywrap_core #(parameter MEM_BITS = 11)
CTRL_MKM_RD_START:
begin
- keywrap_core_ctrl_new = CTRL_MKM_RD_END;
+ mkm_init_op = 1'h1;
+ keywrap_core_ctrl_new = CTRL_MKM_RD_WAIT0;
keywrap_core_ctrl_we = 1'h1;
end
+ CTRL_MKM_RD_WAIT0:
+ begin
+ if (mkm_ready)
+ // MKM should have been initialized.
+ if (mkey_mstatus)
+ begin
+ // Read master key from mkm.
+ keywrap_core_ctrl_new = CTRL_MKM_RD_END;
+ keywrap_core_ctrl_we = 1'h1;
+ end
+ else
+ begin
+ // Read master key status from mkm.
+ mkm_read_op = 1'h1;
+ mkm_addr = MKM_STATUS_WORD;
+ keywrap_core_ctrl_new = CTRL_MKM_RD_STATUS;
+ keywrap_core_ctrl_we = 1'h1;
+ end
+ end
+
+
+ CTRL_MKM_RD_STATUS:
+ begin
+ if (mkm_ready)
+ begin
+ // status should have been read.
+ mkm_status_we = 1'h1;
+ keywrap_core_ctrl_new = CTRL_MKM_RD_END;
+ keywrap_core_ctrl_we = 1'h1;
+ end
+ end
+
+
CTRL_MKM_RD_END:
begin
ready_new = 1'h1;
@@ -653,11 +691,22 @@ module keywrap_core #(parameter MEM_BITS = 11)
CTRL_MKM_WR_START:
begin
- keywrap_core_ctrl_new = CTRL_MKM_WR_END;
+ mkm_init_op = 1'h1;
+ keywrap_core_ctrl_new = CTRL_MKM_WR_WAIT0;
keywrap_core_ctrl_we = 1'h1;
end
+ CTRL_MKM_WR_WAIT0:
+ begin
+ if (mkm_ready)
+ begin
+ keywrap_core_ctrl_new = CTRL_MKM_WR_END;
+ keywrap_core_ctrl_we = 1'h1;
+ end
+ end
+
+
CTRL_MKM_WR_END:
begin
ready_new = 1'h1;
diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v
index 4b94b26..27a2e91 100644
--- a/src/tb/tb_keywrap_core.v
+++ b/src/tb/tb_keywrap_core.v
@@ -67,11 +67,15 @@ module tb_keywrap_core();
reg tb_read;
reg tb_write;
reg tb_encdec;
+ reg tb_mkey_mstatus;
wire tb_ready;
wire tb_valid;
reg [(RLEN_BITS - 1) : 0] tb_rlen;
reg [255 : 0] tb_key;
+ reg [31 : 0] tb_status;
reg tb_keylen;
+ wire [255 : 0] tb_mkey;
+ wire [31 : 0] tb_mstatus;
reg [63 : 0] tb_a_init;
wire [63 : 0] tb_a_result;
reg tb_api_we;
@@ -102,7 +106,8 @@ module tb_keywrap_core();
.next(tb_next),
.read(tb_read),
.write(tb_write),
- .encdec(tb_encdec),
+ .mkey_mstatus(tb_mkey_mstatus),
+ .encdec(tb_encdec),
.ready(tb_ready),
.valid(tb_valid),
@@ -110,6 +115,9 @@ module tb_keywrap_core();
.rlen(tb_rlen),
.key(tb_key),
.keylen(tb_keylen),
+ .status(tb_status),
+ .mkey(tb_mkey),
+ .mstatus(tb_mstatus),
.a_init(tb_a_init),
.a_result(tb_a_result),
@@ -161,18 +169,20 @@ module tb_keywrap_core();
tb_clk = 0;
tb_reset_n = 0;
- tb_init = 0;
- tb_next = 0;
- tb_read = 0;
- tb_write = 0;
- tb_encdec = 0;
- tb_rlen = 13'h0;
- tb_key = 256'h0;
- tb_keylen = 0;
- tb_a_init = 64'h0;
- tb_api_we = 0;
- tb_api_addr = 14'h0;
- tb_api_wr_data = 32'h0;
+ tb_init = 0;
+ tb_next = 0;
+ tb_read = 0;
+ tb_write = 0;
+ tb_encdec = 0;
+ tb_mkey_mstatus = 0;
+ tb_rlen = 13'h0;
+ tb_key = 256'h0;
+ tb_status = 32'h0;
+ tb_keylen = 0;
+ tb_a_init = 64'h0;
+ tb_api_we = 0;
+ tb_api_addr = 14'h0;
+ tb_api_wr_data = 32'h0;
#(CLK_PERIOD * 10);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 22:35:18 +0000