diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/keywrap.v | 49 | ||||
| -rw-r--r-- | src/rtl/keywrap_core.v | 36 |
2 files changed, 49 insertions, 36 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index b394c9c..5604ce4 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -151,16 +151,11 @@ module keywrap #(parameter ADDR_BITS = 13) wire core_ready; wire core_valid; wire [255 : 0] core_key; + wire [255 : 0] core_read_key; wire [63 : 0] core_a_init; wire [63 : 0] core_a_result; wire [31 : 0] core_api_rd_data; - reg mem_cs; - reg mem_we; - reg [7 : 0] mem_address; - reg [31 : 0] mem_write_data; - wire [31 : 0] mem_read_data; - //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -184,6 +179,11 @@ module keywrap #(parameter ADDR_BITS = 13) .clk(clk), .reset_n(reset_n), + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), + .init(init_reg), .next(next_reg), .encdec(encdec_reg), @@ -195,6 +195,7 @@ module keywrap #(parameter ADDR_BITS = 13) .key(core_key), .keylen(keylen_reg), + .read_key(core_read_key), .a_init(core_a_init), .a_result(core_a_result), @@ -205,22 +206,6 @@ module keywrap #(parameter ADDR_BITS = 13) .api_rd_data(core_api_rd_data) ); - mkmif memory( - .clk(clk), - .reset_n(reset_n), - - .spi_sclk(mkm_spi_sclk), - .spi_cs_n(mkm_spi_cs_n), - .spi_do(mkm_spi_do), - .spi_di(mkm_spi_di), - - .cs(mem_cs), - .we(mem_we), - .address(mem_address), - .write_data(mem_write_data), - .read_data(mem_read_data) - ); - //---------------------------------------------------------------- // reg_update @@ -303,6 +288,7 @@ module keywrap #(parameter ADDR_BITS = 13) begin if (we) begin + // Write access if (address == {{PAD{1'h0}}, ADDR_CTRL}) begin init_new = write_data[CTRL_INIT_BIT]; @@ -354,23 +340,14 @@ module keywrap #(parameter ADDR_BITS = 13) if (address == {{PAD{1'h0}}, ADDR_A1}) api_rd_delay_new = core_a_result[31 : 0]; + + // Not correct read key mux. + if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && + (address <= {{PAD{1'h0}}, ADDR_KEY7})) + api_rd_delay_new = core_read_key[031 : 000]; end // else: !if(we) end // if (cs) end // block: api - - - //---------------------------------------------------------------- - // mkmif_ctrl - // Logic needed to handle the integratrion of the mkmif - //---------------------------------------------------------------- - always @* - begin : mkmif_ctrl - mem_cs = 1'h0; - mem_we = 1'h0; - mem_address = 8'h0; - mem_write_data = 32'h0; - end - endmodule // keywrap //====================================================================== diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index d1e63b0..e9a7177 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -45,6 +45,11 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire clk, input wire reset_n, + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + input wire init, input wire next, input wire encdec, @@ -56,6 +61,7 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire [255 : 0] key, input wire keylen, + output wire [255 : 0] read_key, input wire [63 : 0] a_init, output wire [63 : 0] a_result, @@ -84,6 +90,9 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam CTRL_NEXT_UCHECK = 4'h9; localparam CTRL_NEXT_FINALIZE = 4'ha; + // If set to one, will allow read access to key memory. + localparam DEBUG_MKM_READ = 1'h1; + //---------------------------------------------------------------- // Registers and memories including control signals. @@ -139,6 +148,12 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; + reg mkm_cs; + reg mkm_we; + reg [7 : 0] mkm_address; + reg [31 : 0] mkm_write_data; + wire [31 : 0] mkm_read_data; + //---------------------------------------------------------------- // Instantiations. @@ -178,6 +193,23 @@ module keywrap_core #(parameter MEM_BITS = 11) ); + mkmif mkm( + .clk(clk), + .reset_n(reset_n), + + .spi_sclk(mkm_spi_sclk), + .spi_cs_n(mkm_spi_cs_n), + .spi_do(mkm_spi_do), + .spi_di(mkm_spi_di), + + .cs(mkm_cs), + .we(mkm_we), + .address(mkm_address), + .write_data(mkm_write_data), + .read_data(mkm_read_data) + ); + + //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- @@ -356,6 +388,10 @@ module keywrap_core #(parameter MEM_BITS = 11) iteration_ctr_dec = 1'h0; iteration_ctr_set = 1'h0; iteration_ctr_rst = 1'h0; + mkm_cs = 1'h0; + mkm_we = 1'h0; + mkm_address = 8'h0; + mkm_write_data = 32'h0; keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h0; |