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author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-11-13 13:42:16 +0100 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-11-13 13:42:16 +0100 |
commit | 038eb4f4f4e5ca2cf6ad80e02091df0a34e6bde3 (patch) | |
tree | 117cfb29fdc9baa0d05d9f958aba96325d7e1a52 | |
parent | 42d63504f02f895a7b89dc164571c4b0d21cf8d4 (diff) |
Adding README that describes the purpose of the dir and how to get the vendor specific memory model we need here.
-rw-r--r-- | src/tech/README.md | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/tech/README.md b/src/tech/README.md new file mode 100644 index 0000000..0e04542 --- /dev/null +++ b/src/tech/README.md @@ -0,0 +1,14 @@ +README.md +========= +This dir is where the vendor specific Verilog memory model should be +stored. + +The memory used is the [Microchip +23K640](https://www.microchip.com/wwwproducts/en/23A640) a 64kbit, +SPI-connected serial SRAM. + +The Verilog memory model can be downloaded from that webpage or [by +clicking on this link](http://ww1.microchip.com/downloads/en/DeviceDoc/23x640_Verilog_Model.zip). + +Download and unzip the file in this directory. This should produce two +files, 23A640.v and 23K640.v. The one needed for simulation is 23K640.v |