//======================================================================
//
// tb_keywrap_mkm.v
// ----------------
// Testbench for the mkmif wrapper in keywrap.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
// We need this since the specific memory module sets timescale.
`timescale 1ns/10ps
module tb_keywrap_mkmif();
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Variables, regs and wires.
//----------------------------------------------------------------
integer cycle_ctr;
integer error_ctr;
integer tc_ctr;
integer show_spi;
integer show_dut_state;
reg tb_clk;
reg tb_reset_n;
wire tb_mkm_spi_sclk;
wire tb_mkm_spi_cs_n;
wire tb_mkm_spi_do;
wire tb_mkm_spi_di;
reg tb_init;
reg tb_read;
reg tb_write;
reg tb_key_status;
wire tb_ready;
reg [31 : 0] tb_wr_status;
wire [31 : 0] tb_rd_status;
reg [255 : 0] tb_wr_key;
wire [255 : 0] tb_rd_key;
wire mem_hold_n = 1'b1;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
keywrap_mkmif dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.mkm_spi_sclk(tb_mkm_spi_sclk),
.mkm_spi_cs_n(tb_mkm_spi_cs_n),
.mkm_spi_do(tb_mkm_spi_do),
.mkm_spi_di(tb_mkm_spi_di),
.init(tb_init),
.read(tb_read),
.write(tb_write),
.key_status(tb_key_status),
.ready(tb_ready),
.wr_status(tb_wr_status),
.rd_status(tb_rd_status),
.wr_key(tb_wr_key),
.rd_key(tb_rd_key)
);
//----------------------------------------------------------------
// Memory model. See README.md in src/tech for info on how
// to get the vendor specific model needed here.
//----------------------------------------------------------------
M23K640 memory(.SI(tb_mkm_spi_di),
.SO(tb_mkm_spi_do),
.SCK(tb_mkm_spi_sclk),
.CS_N(tb_mkm_spi_cs_n),
.HOLD_N(mem_hold_n),
.RESET(tb_reset_n));
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
$display("cycle: %08d", cycle_ctr);
if (show_dut_state)
begin
$display("init: 0x%01x read: 0x%01x write: 0x%01x key_status: 0x%01x",
dut.init, dut.read, dut.write, dut.key_status);
$display("ready: 0x%01x ctrl_state: 0x%02x", dut.ready, dut.keywrap_mkmif_ctrl_reg);
end
if (show_spi)
begin
$display("spi_clk: 0x%01x, spi_cs_n: 0x%01x, spi_do: 0x%01x, spi_di: 0x%01x",
tb_mkm_spi_sclk, tb_mkm_spi_cs_n, tb_mkm_spi_do, tb_mkm_spi_di);
$display();
$display();
end
#(CLK_PERIOD);
end
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
show_spi = 0;
show_dut_state = 1;
tb_clk = 1'h0;
tb_reset_n = 1'h1;
tb_init = 1'h0;
tb_read = 1'h0;
tb_write = 1'h0;
tb_key_status = 1'h0;
tb_wr_status = 32'h0;
tb_wr_key = 256'h0;
#(CLK_PERIOD);
end
endtask // init_sim
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("Asserting reset.");
$display();
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("Deasserting reset.");
$display();
end
endtask // reset_dut
//----------------------------------------------------------------
// wait_ready()
//
// Wait for ready to be asserted.
//----------------------------------------------------------------
task wait_ready;
begin
#(2 * CLK_PERIOD);
while (!tb_ready)
#(CLK_PERIOD);
$display("Ready has been set.");
$display();
end
endtask // wait_ready
//----------------------------------------------------------------
// test_init_mem
//----------------------------------------------------------------
task test_init_mem;
begin
tc_ctr = tc_ctr + 1;
$display("TEST INIT-MEM START");
$display("Check that the memory is configured when pulling init.");
$display();
show_spi = 1;
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
show_spi = 0;
$display("TEST INIT-MEM END");
$display("");
end
endtask // test_init_mem
//----------------------------------------------------------------
// test_write_status
//----------------------------------------------------------------
task test_write_status;
begin
tc_ctr = tc_ctr + 1;
$display("TEST WRITE-STATUS START");
$display("Check that we can write the key status word.");
// Observe SPI for a number of cycles. Reset the DUT during observation.
show_spi = 1;
#(10 * CLK_PERIOD);
$display("Trying to write 0xdeadbeef to status address.");
tb_wr_status = 32'hdeadbeef;
tb_key_status = 1'h0;
tb_write = 1'h1;
#(CLK_PERIOD);
tb_write = 1'h0;
wait_ready();
show_spi = 0;
$display("TEST WRITE-STATUS END");
$display("");
end
endtask // test_write_status
//----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for Keywrap mkmif integration started =-");
$display(" ====================================================");
$display("");
init_sim();
reset_dut();
test_init_mem();
test_write_status();
$display("");
$display("*** Keywrap mkmif integration testbench done. ***");
$finish;
end // main
endmodule // tb_keywrap_mkmif
//======================================================================
// EOF tb_keywrap_mkmif.v
//======================================================================
