//======================================================================
//
// keywrap_core.v
// --------------
// Core that tries to implement AES KEY WRAP as specified in
// RFC 3394 and extended with padding in RFC 5649.
// Experimental core at the moment. Does Not Work.
// The maximum wrap object size is 64 kByte.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module keywrap_core (
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire encdec,
output wire ready,
output wire valid,
input wire [12 : 0] rlen,
input wire [255 : 0] key,
input wire keylen,
input wire api_cs,
input wire api_we,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data
);
//----------------------------------------------------------------
// Paramenters and local defines.
//----------------------------------------------------------------
localparam OUTER_LOOP_MAX = 6;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_NEXT = 3'h2;
localparam RFC5649_A_IV = 32'ha65959a6;
//----------------------------------------------------------------
// Registers and memories including control signals.
//----------------------------------------------------------------
reg [63 : 0] a_reg;
reg [63 : 0] a_new;
reg a_we;
reg a_init;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [13 : 0] api_addr_ctr_reg;
reg [13 : 0] api_addr_ctr_new;
reg api_addr_ctr_we;
reg api_addr_ctr_inc;
reg api_addr_ctr_rst;
reg [12 : 0] block_ctr_reg;
reg [12 : 0] block_ctr_new;
reg block_ctr_we;
reg block_ctr_inc;
reg block_ctr_rst;
reg [2 : 0] iteration_ctr_reg;
reg [2 : 0] iteration_ctr_new;
reg iteration_ctr_we;
reg iteration_ctr_inc;
reg iteration_ctr_dec;
reg iteration_ctr_set;
reg iteration_ctr_rst;
reg [2 : 0] keywrap_core_ctrl_reg;
reg [2 : 0] keywrap_core_ctrl_new;
reg keywrap_core_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg aes_encdec;
reg aes_init;
reg aes_next;
wire aes_ready;
reg [127 : 0] aes_block;
wire [127 : 0] aes_result;
wire aes_valid;
reg core_we;
reg [12 : 0] core_addr;
reg [63 : 0] core_wr_data;
wire [63 : 0] core_rd_data;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
keywrap_mem mem(
.clk(clk),
.api_we(api_we),
.api_addr(api_addr_ctr_reg),
.api_wr_data(api_wr_data),
.api_rd_data(api_rd_data),
.core_we(core_we),
.core_addr(core_addr),
.core_wr_data(core_wr_data),
.core_rd_data(core_rd_data)
);
aes_core aes(
.clk(clk),
.reset_n(reset_n),
.encdec(aes_encdec),
.init(aes_init),
.next(aes_next),
.key(key),
.keylen(keylen),
.block(aes_block),
.ready(aes_ready),
.result(aes_result),
.result_valid(aes_valid)
);
//----------------------------------------------------------------
// Assignments for ports.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
keywrap_core_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (keywrap_core_ctrl_we)
keywrap_core_ctrl_reg <= keywrap_core_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// api_addr_ctr
//----------------------------------------------------------------
always @*
begin : api_addr_ctr
api_addr_ctr_new = 14'h0;
api_addr_ctr_we = 1'h0;
if (api_addr_ctr_rst)
begin
api_addr_ctr_new = 14'h0;
api_addr_ctr_we = 1'h1;
end
if (api_addr_ctr_inc)
begin
api_addr_ctr_new = api_addr_ctr_reg + 1'h1;
api_addr_ctr_we = 1'h1;
end
end
//----------------------------------------------------------------
// block_ctr
//----------------------------------------------------------------
always @*
begin : block_ctr
block_ctr_new = 13'h0;
block_ctr_we = 1'h0;
if (block_ctr_rst)
begin
block_ctr_new = 13'h0;
block_ctr_we = 1'h1;
end
if (block_ctr_inc)
begin
block_ctr_new = block_ctr_reg + 1'h1;
block_ctr_we = 1'h1;
end
end
//----------------------------------------------------------------
// iteration_ctr
//----------------------------------------------------------------
always @*
begin : iteration_ctr
iteration_ctr_new = 3'h0;
iteration_ctr_we = 1'h0;
if (iteration_ctr_rst)
begin
iteration_ctr_new = 3'h0;
iteration_ctr_we = 1'h1;
end
if (iteration_ctr_set)
begin
iteration_ctr_new = 3'h5;
iteration_ctr_we = 1'h1;
end
if (iteration_ctr_dec)
begin
iteration_ctr_new = iteration_ctr_reg + 1'h1;
iteration_ctr_we = 1'h1;
end
if (iteration_ctr_inc)
begin
iteration_ctr_new = iteration_ctr_reg + 1'h1;
iteration_ctr_we = 1'h1;
end
end
//----------------------------------------------------------------
// keywrap_core_ctrl
//----------------------------------------------------------------
always @*
begin : keywrap_core_ctrl
aes_encdec = 0;
aes_init = 0;
aes_next = 0;
block_ctr_inc = 0;
block_ctr_rst = 0;
iteration_ctr_inc = 0;
iteration_ctr_dec = 0;
iteration_ctr_set = 0;
iteration_ctr_rst = 0;
case (keywrap_core_ctrl_reg)
CTRL_IDLE:
begin
end
default:
begin
end
endcase // case (keywrap_core_ctrl_reg)
end // keywrap_core_ctrl
endmodule // keywrap_core
//======================================================================
// EOF keywrap_core.v
//======================================================================
