| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-04-02 | (1) Added a state in the write fifo machine to actually drop request between ... | Joachim Strömbergson |
| 2015-04-02 | Fixed syntax and added init functionality for testing the dut. | Joachim Strömbergson |
| 2015-04-01 | Adding initial version of testbench for the csprng fifo. | Joachim Strömbergson |
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index : core/rng/trng | |
| True Random Number Generator core implemented in Verilog | git repositories |
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