core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2015-09-07	Adding a new task that reads out a given number of random data words from the...	Joachim Strömbergson
2015-08-27	Removed the temporary task for generating seeds that is obsoleted by the seed...	Joachim Strömbergson
2015-08-27	Added process to generate need seeds with differentg patterns and communicate...	Joachim Strömbergson
2015-08-26	(1) Removed obsolete dump of values from the monitor. (2) Changed to using pr...	Joachim Strömbergson
2015-08-26	Adding test case for verifying reseed functionality in csprng.	Joachim Strömbergson
2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code a...	Joachim Strömbergson
2014-11-20	Updates of variable names to matched changed instance name and new fifo.	Joachim Strömbergson
2014-10-02	Updating testbenches to match new interfaces and use the api to read and writ...	Joachim Strömbergson
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson