diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2014-10-02 14:25:46 +0200 |
---|---|---|
committer | Joachim StroĢmbergson <joachim@secworks.se> | 2014-10-02 14:25:46 +0200 |
commit | fe96fc8106b88b26311a5f911f42c73c66b977d9 (patch) | |
tree | 21bc5bd0eeac81de9312d1b25eacb3985eeea37f /src/tb/tb_csprng.v | |
parent | 6d3268df973d4175e59daf44f601cef36c90c9ac (diff) |
Updating testbenches to match new interfaces and use the api to read and write data.
Diffstat (limited to 'src/tb/tb_csprng.v')
-rw-r--r-- | src/tb/tb_csprng.v | 147 |
1 files changed, 106 insertions, 41 deletions
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v index 10a7992..e92828d 100644 --- a/src/tb/tb_csprng.v +++ b/src/tb/tb_csprng.v @@ -65,21 +65,32 @@ module tb_csprng(); reg tb_clk; reg tb_reset_n; - reg tb_debug_mode; - reg [4 : 0] tb_num_rounds; - reg [63 : 0] tb_num_blocks; - reg tb_seed; - reg tb_enable; + + reg tb_cs; + reg tb_we; + reg [7 : 0] tb_address; + reg [31 : 0] tb_write_data; + wire [31 : 0] tb_read_data; + wire tb_error; + + reg tb_discard; + reg tb_test_mode; + wire tb_ready; wire tb_more_seed; - wire tb_error; + wire tb_security_error; reg tb_seed_syn; reg [511 : 0] tb_seed_data; wire tb_seed_ack; - wire tb_rnd_syn; wire [31: 0] tb_rnd_data; + wire tb_rnd_syn; reg tb_rnd_ack; + wire [7 : 0] tb_debug; + reg tb_debug_update; + + reg [31 : 0] read_data; + //---------------------------------------------------------------- // Device Under Test. @@ -88,22 +99,25 @@ module tb_csprng(); .clk(tb_clk), .reset_n(tb_reset_n), - .debug_mode(tb_debug_mode), - .num_rounds(tb_num_rounds), - .num_blocks(tb_num_blocks), - .seed(tb_seed), - .enable(tb_enable), - .more_seed(tb_more_seed), - .ready(tb_ready), + .cs(tb_cs), + .we(tb_we), + .address(tb_address), + .write_data(tb_write_data), + .read_data(tb_read_data), .error(tb_error), - .seed_syn(tb_seed_syn), + .discard(tb_discard), + .test_mode(tb_test_mode), + + .more_seed(tb_more_seed), + .security_error(tb_security_error), + .seed_data(tb_seed_data), + .seed_syn(tb_seed_syn), .seed_ack(tb_seed_ack), - .rnd_syn(tb_rnd_syn), - .rnd_data(tb_rnd_data), - .rnd_ack(tb_rnd_ack) + .debug(tb_debug), + .debug_update(tb_debug_update) ); @@ -149,12 +163,10 @@ module tb_csprng(); $display("State of DUT"); $display("------------"); $display("Inputs:"); - $display("debug_mode = 0x%01x, seed = 0x%01x, enable = 0x%01x", - dut.debug_mode, dut.seed, dut.enable); - $display("ready = 0x%01x, error = 0x%01x", - dut.ready, dut.error); + $display("test_mode = 0x%01x, seed = 0x%01x, enable = 0x%01x", + dut.test_mode, dut.seed_reg, dut.enable_reg); $display("num_rounds = 0x%02x, num_blocks = 0x%016x", - dut.num_rounds, dut.num_blocks); + dut.num_rounds_reg, dut.num_blocks); $display("seed_syn = 0x%01x, seed_ack = 0x%01x, seed_data = 0x%064x", dut.seed_syn, dut.seed_ack, dut.seed_data); $display(""); @@ -190,6 +202,56 @@ module tb_csprng(); //---------------------------------------------------------------- + // write_word() + // + // Write the given word to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_word(input [11 : 0] address, + input [31 : 0] word); + begin + if (DEBUG) + begin + $display("*** Writing 0x%08x to 0x%02x.", word, address); + $display(""); + end + + tb_address = address; + tb_write_data = word; + tb_cs = 1; + tb_we = 1; + #(2 * CLK_PERIOD); + tb_cs = 0; + tb_we = 0; + end + endtask // write_word + + + //---------------------------------------------------------------- + // read_word() + // + // Read a data word from the given address in the DUT. + // the word read will be available in the global variable + // read_data. + //---------------------------------------------------------------- + task read_word(input [11 : 0] address); + begin + tb_address = address; + tb_cs = 1; + tb_we = 0; + #(CLK_PERIOD); + read_data = tb_read_data; + tb_cs = 0; + + if (DEBUG) + begin + $display("*** Reading 0x%08x from 0x%02x.", read_data, address); + $display(""); + end + end + endtask // read_word + + + //---------------------------------------------------------------- // reset_dut() // // Toggle reset to put the DUT into a well known state. @@ -234,20 +296,25 @@ module tb_csprng(); //---------------------------------------------------------------- task init_sim(); begin - cycle_ctr = 0; - error_ctr = 0; - tc_ctr = 0; - - tb_clk = 0; - tb_reset_n = 1; - tb_debug_mode = 0; - tb_num_rounds = 5'h00; - tb_num_blocks = 64'h0000000000000000; - tb_seed = 0; - tb_enable = 0; - tb_seed_syn = 0; - tb_seed_data = {16{32'h00000000}}; - tb_rnd_ack = 0; + cycle_ctr = 0; + error_ctr = 0; + tc_ctr = 0; + + tb_clk = 0; + tb_reset_n = 1; + + tb_cs = 0; + tb_we = 0; + tb_address = 8'h00; + tb_write_data = 32'h00000000; + + tb_discard = 0; + tb_test_mode = 0; + + tb_seed_syn = 0; + tb_seed_data = {16{32'h00000000}}; + tb_rnd_ack = 0; + tb_debug_update = 0; end endtask // init_sim @@ -261,11 +328,9 @@ module tb_csprng(); task tc1_test_init_cipher(); begin $display("*** TC1: Test automatic init of cipher started."); - tb_num_blocks = 64'h0000000000000004; - tb_seed_syn = 1; + // tb_num_blocks = 64'h0000000000000004; tb_seed_data = {8{64'haaaaaaaa55555555}}; - tb_enable = 1; - tb_num_rounds = 5'h08; + // tb_num_rounds = 5'h08; tb_rnd_ack = 1; #(2000 * CLK_PERIOD); |