diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2014-03-17 15:37:27 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2014-03-17 15:37:27 +0100 |
| commit | fca501de1b8b3d1dca36d96adc00ff644fe68eae (patch) | |
| tree | 3c7330b4eb145f402fb26bcef156ede530c43691 /toolruns/quartus/terasic_c5g/coretest_hashes.sdc | |
| parent | 2608109e952723a71e966e8993278bf3313aa78a (diff) | |
Adding project, assignment and clock setup files for Quartus and the TerasIC C5G board.
Diffstat (limited to 'toolruns/quartus/terasic_c5g/coretest_hashes.sdc')
| -rw-r--r-- | toolruns/quartus/terasic_c5g/coretest_hashes.sdc | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.sdc b/toolruns/quartus/terasic_c5g/coretest_hashes.sdc new file mode 100644 index 0000000..93e1282 --- /dev/null +++ b/toolruns/quartus/terasic_c5g/coretest_hashes.sdc @@ -0,0 +1,40 @@ +#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.
+#
+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
+#
+#************************************************************
+
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "clk" -period 20.000ns [get_ports {clk}]
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
|