| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-11-14 | Catch up with other branch merges. | Paul Selkirk |
| 2015-09-29 | Attempting to optimize out the one-cycle delay didn't work, relatively | Rob Austein |
| 2015-09-29 | Add support for error_wire and block_memory options. | Rob Austein |
| 2015-09-29 | Sick hacks to compensate for sparse MUX within TRNG core. | Rob Austein |
| 2015-09-28 | Handle reset high/low logic in the config file. Connect error signals. | Rob Austein |
| 2015-09-27 | Wedge modexps6 into the addressing scheme. Adjust timing of other | Rob Austein |
| 2015-09-26 | Sorted out reset pins (I think). Seems our various core authors have | Rob Austein |
| 2015-06-10 | generate core_selector, probe FPGA for cores at software startup | Paul Selkirk |
 |
index : core/platform/novena | |
| Platform-specific files for the Novena PVT1 | git repositories |
| aboutsummaryrefslogtreecommitdiff |