diff options
author | Rob Austein <sra@hactrn.net> | 2015-09-29 00:04:01 -0400 |
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committer | Rob Austein <sra@hactrn.net> | 2015-09-29 00:04:01 -0400 |
commit | c421ca5e30120861006a6a0ca0ba3f23b14d88ed (patch) | |
tree | 9e1f04d602fa18e326cf62bc5cc08101e7ac045a /config/core_selector.v | |
parent | ff4cf7a0530218cb86a860c803e6fccdafcff385 (diff) |
Sick hacks to compensate for sparse MUX within TRNG core.
Diffstat (limited to 'config/core_selector.v')
-rw-r--r-- | config/core_selector.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/config/core_selector.v b/config/core_selector.v index cc7ca14..90b688e 100644 --- a/config/core_selector.v +++ b/config/core_selector.v @@ -34,11 +34,11 @@ module core_selector localparam CORE_ADDR_SHA256 = 9'h02; localparam CORE_ADDR_AES = 9'h03; localparam CORE_ADDR_TRNG = 9'h04; - localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h05; - localparam CORE_ADDR_ROSC_ENTROPY = 9'h06; - localparam CORE_ADDR_TRNG_MIXER = 9'h07; - localparam CORE_ADDR_TRNG_CSPRNG = 9'h08; - localparam CORE_ADDR_MODEXP = 9'h09; + localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h09; + localparam CORE_ADDR_ROSC_ENTROPY = 9'h0a; + localparam CORE_ADDR_TRNG_MIXER = 9'h0e; + localparam CORE_ADDR_TRNG_CSPRNG = 9'h0f; + localparam CORE_ADDR_MODEXP = 9'h14; //---------------------------------------------------------------- @@ -148,7 +148,7 @@ module core_selector //---------------------------------------------------------------- // TRNG //---------------------------------------------------------------- - wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG_CSPRNG); + wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG + 9'h0f); wire [31: 0] read_data_trng; wire error_trng; wire [3:0] trng_prefix = addr_core_num[3:0] - CORE_ADDR_TRNG; |