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-rw-r--r--eim/build/Makefile12
1 files changed, 6 insertions, 6 deletions
diff --git a/eim/build/Makefile b/eim/build/Makefile
index 8b984a2..a6b6d33 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -17,32 +17,32 @@ top_module = novena_top
isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
-#ucf ?= ../ucf/$(project)-dev_bridge_board.ucf
all: $(project).bit
# Build the default core_selector if it doesn't already exist.
CONFIG = $(CORE_TREE)/platform/common/config
+CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b novena
core_selector.v core_vfiles.mk:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg
+ $(CONFIG_GEN) -p rsa
# Build some different configurations
bare:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+ $(CONFIG_GEN) -p bare
$(MAKE) project=$(project)_bare ucf=$(ucf)
trng:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+ $(CONFIG_GEN) -p trng
$(MAKE) project=$(project)_trng ucf=$(ucf)
hash:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+ $(CONFIG_GEN) -p hash
$(MAKE) project=$(project)_hash ucf=$(ucf)
rsa:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+ $(CONFIG_GEN) -p rsa
$(MAKE) project=$(project)_rsa ucf=$(ucf)
# Verilog files that always go with builds on this platform.