diff options
Diffstat (limited to 'common')
| -rw-r--r-- | common/rtl/novena_clkmgr.v | 77 | ||||
| -rw-r--r-- | common/rtl/novena_dcm_spartan6.v | 173 |
2 files changed, 210 insertions, 40 deletions
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v index 97db451..38a89eb 100644 --- a/common/rtl/novena_clkmgr.v +++ b/common/rtl/novena_clkmgr.v @@ -42,47 +42,40 @@ module novena_clkmgr input wire gclk_p, // signal from clock pins input wire gclk_n, // - input wire reset_mcu_b, // cpu reset (async) + input wire reset_mcu_b, // cpu reset (async, active-low) output wire sys_clk, // buffered system clock output - output wire sys_rst // system reset output (sync) + output wire sys_rst_n // system reset output (async set, sync clear, active-low) ); - // - // Ports - // - - - // - // IBUFGDS - // - (* BUFFER_TYPE="NONE" *) - wire gclk; - - IBUFGDS IBUFGDS_gclk - ( - .I(gclk_p), - .IB(gclk_n), - .O(gclk) - ); - // - // DCM + // Wrapper for Xilinx-specific DCM (Digital Clock Managar) primitive. // - wire dcm_reset; // dcm reset - wire dcm_locked; // output clock valid - wire gclk_missing; // no input clock - - clkmgr_dcm dcm - ( - .CLK_IN1(gclk), - .RESET(dcm_reset), - .INPUT_CLK_STOPPED(gclk_missing), - - .CLK_OUT1(sys_clk), - .CLK_VALID(dcm_locked) - ); + + wire gclk; // buffered input clock + wire dcm_reset; // dcm reset + wire dcm_locked; // output clock valid + wire gclk_missing; // missing input clock + + novena_dcm_spartan6 # + ( + .CLK_OUT_MUL (2), // 2..32 + .CLK_OUT_DIV (2) // 1..32 + ) + dcm_s6 + ( + .clk_in_p(gclk_p), + .clk_in_n(gclk_n), + + .reset_in(dcm_reset), + + .gclk_out(gclk), + .gclk_missing_out(gclk_missing), + + .clk_out(sys_clk), + .clk_valid_out (dcm_locked) + ); // @@ -90,7 +83,8 @@ module novena_clkmgr // /* DCM should be reset on power-up, when input clock is stopped or when the - * CPU gets reset. + * CPU gets reset. Note that DCM requires active-high reset, so the shift + * register is preloaded with 1's and gradually filled with 0's. */ reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register @@ -109,18 +103,21 @@ module novena_clkmgr // System Reset Logic // - /* System reset is asserted for 16 cycles whenever DCM aquires lock. */ + /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note that system + * reset is active-low, so the shift register is preloaded with 0's and gradually filled + * with 1's afterwards. + */ - reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register + reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) // if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) - sys_rst_shreg <= {16{1'b1}}; + sys_rst_shreg <= {16{1'b0}}; else if (dcm_locked == 1'b1) - sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; + sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1}; - assign sys_rst = sys_rst_shreg[15]; + assign sys_rst_n = sys_rst_shreg[15]; endmodule diff --git a/common/rtl/novena_dcm_spartan6.v b/common/rtl/novena_dcm_spartan6.v new file mode 100644 index 0000000..ab60254 --- /dev/null +++ b/common/rtl/novena_dcm_spartan6.v @@ -0,0 +1,173 @@ +//====================================================================== +// +// novena_dcm_spartan6.v +// --------------------- +// Wrapper file for Xilinx-specific DCM_SP primitive and supporting
+// vendor-specific stuff. This wrapper can be used to get rid of
+// "Clocking Wizard" IP core and associated coregen pain.
+// +// +// Author: Pavel Shatov +// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== +
+`timescale 1ns / 1ps
+
+module novena_dcm_spartan6
+ (
+ input wire clk_in_p,
+ input wire clk_in_n,
+ + input wire reset_in, +
+ output wire gclk_out, + output wire gclk_missing_out, + + output wire clk_out, + output wire clk_valid_out
+ );
+
+
+ // + // Parameters + // + parameter CLK_OUT_MUL = 2; // multiply factor for output clock frequency (2..32) + parameter CLK_OUT_DIV = 2; // divide factor for output clock frequency (1..32)
+
+ //
+ // IBUFGDS
+ //
+
+ /* Xilinx-specific primitive to handle LVDS input signal. */
+
+ (* BUFFER_TYPE="NONE" *)
+ wire clk_in;
+ + IBUFGDS IBUFGDS_gclk + ( + .I(clk_in_p), + .IB(clk_in_n), + .O(clk_in) + );
+
+
+ // + // DCM_SP + //
+
+ /* Xilinx-specific primitive. */
+ + wire dcm_clk_0; // primary (1:1) output + wire dcm_clk_feedback; // PLL feedback path + wire dcm_clk_fx; // synthesized frequency + wire dcm_locked_int; // locked flag + wire [ 7: 0] dcm_status_int; // status of DCM + + DCM_SP # + ( + .STARTUP_WAIT ("FALSE"), + .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), + .CLK_FEEDBACK ("1X"), + + .PHASE_SHIFT (0), + .CLKOUT_PHASE_SHIFT ("NONE"), + + .CLKIN_PERIOD (20.0), // 50 MHz => 20 ns + .CLKIN_DIVIDE_BY_2 ("FALSE"), + + .CLKDV_DIVIDE (5.000), + .CLKFX_MULTIPLY (CLK_OUT_MUL), + .CLKFX_DIVIDE (CLK_OUT_DIV) + ) + DCM_SP_inst + ( + .RST (reset_in), + + .CLKIN (gclk_out), + .CLKFB (dcm_clk_feedback), + .CLKDV (), + + .CLK0 (dcm_clk_0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + + .CLK2X (), + .CLK2X180 (), + + .CLKFX (dcm_clk_fx), + .CLKFX180 (), + + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + + .LOCKED (dcm_locked_int), + .STATUS (dcm_status_int), + + .DSSEN (1'b0) + ); + + + // + // Mapping + //
+ assign gclk_out = clk_in; + assign gclk_missing_out = dcm_status_int[1]; + assign clk_valid_out = dcm_locked_int & ((dcm_status_int[2:1] == 2'b00) ? 1'b1 : 1'b0); + + + // + // Feedback Path + //
+
+ /* DCM_SP requires BUFG primitive in its feedback path. */
+ + BUFG BUFG_feedback + ( + .I (dcm_clk_0), + .O (dcm_clk_feedback) + ); + + // + // Output Buffer + //
+
+ /* Connect system clock to global clocking network. */
+ + BUFG BUFG_output + ( + .I (dcm_clk_fx), + .O (clk_out) + ); +
+
+endmodule
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