diff options
Diffstat (limited to 'common/rtl/novena_clkmgr.v')
| -rw-r--r-- | common/rtl/novena_clkmgr.v | 77 |
1 files changed, 37 insertions, 40 deletions
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v index 97db451..38a89eb 100644 --- a/common/rtl/novena_clkmgr.v +++ b/common/rtl/novena_clkmgr.v @@ -42,47 +42,40 @@ module novena_clkmgr input wire gclk_p, // signal from clock pins input wire gclk_n, // - input wire reset_mcu_b, // cpu reset (async) + input wire reset_mcu_b, // cpu reset (async, active-low) output wire sys_clk, // buffered system clock output - output wire sys_rst // system reset output (sync) + output wire sys_rst_n // system reset output (async set, sync clear, active-low) ); - // - // Ports - // - - - // - // IBUFGDS - // - (* BUFFER_TYPE="NONE" *) - wire gclk; - - IBUFGDS IBUFGDS_gclk - ( - .I(gclk_p), - .IB(gclk_n), - .O(gclk) - ); - // - // DCM + // Wrapper for Xilinx-specific DCM (Digital Clock Managar) primitive. // - wire dcm_reset; // dcm reset - wire dcm_locked; // output clock valid - wire gclk_missing; // no input clock - - clkmgr_dcm dcm - ( - .CLK_IN1(gclk), - .RESET(dcm_reset), - .INPUT_CLK_STOPPED(gclk_missing), - - .CLK_OUT1(sys_clk), - .CLK_VALID(dcm_locked) - ); + + wire gclk; // buffered input clock + wire dcm_reset; // dcm reset + wire dcm_locked; // output clock valid + wire gclk_missing; // missing input clock + + novena_dcm_spartan6 # + ( + .CLK_OUT_MUL (2), // 2..32 + .CLK_OUT_DIV (2) // 1..32 + ) + dcm_s6 + ( + .clk_in_p(gclk_p), + .clk_in_n(gclk_n), + + .reset_in(dcm_reset), + + .gclk_out(gclk), + .gclk_missing_out(gclk_missing), + + .clk_out(sys_clk), + .clk_valid_out (dcm_locked) + ); // @@ -90,7 +83,8 @@ module novena_clkmgr // /* DCM should be reset on power-up, when input clock is stopped or when the - * CPU gets reset. + * CPU gets reset. Note that DCM requires active-high reset, so the shift + * register is preloaded with 1's and gradually filled with 0's. */ reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register @@ -109,18 +103,21 @@ module novena_clkmgr // System Reset Logic // - /* System reset is asserted for 16 cycles whenever DCM aquires lock. */ + /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note that system + * reset is active-low, so the shift register is preloaded with 0's and gradually filled + * with 1's afterwards. + */ - reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register + reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) // if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) - sys_rst_shreg <= {16{1'b1}}; + sys_rst_shreg <= {16{1'b0}}; else if (dcm_locked == 1'b1) - sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; + sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1}; - assign sys_rst = sys_rst_shreg[15]; + assign sys_rst_n = sys_rst_shreg[15]; endmodule |