1 files changed, 0 insertions, 69 deletions
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
deleted file mode 100644
index e8c0fdf..0000000
--- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
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@@ -1,69 +0,0 @@
-# file : planAhead_rdn.tcl
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
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-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
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-# loss or damage suffered as a result of any action brought
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-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
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-# Applications"). Customer assumes the sole risk and
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-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-set device xc6slx45csg324-3
-set projName clkmgr_dcm
-set design clkmgr_dcm
-set projDir [file dirname [info script]]
-create_project $projName $projDir/results/$projName -part $device -force
-set_property design_mode RTL [current_fileset -srcset]
-set top_module clkmgr_dcm_exdes
-set_property top clkmgr_dcm_exdes [get_property srcset [current_run]]
-add_files -norecurse {../../../clkmgr_dcm.v}
-add_files -norecurse {../../example_design/clkmgr_dcm_exdes.v}
-import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clkmgr_dcm_exdes.xdc}
-synth_design
-opt_design 
-place_design 
-route_design 
-write_sdf -rename_top_module clkmgr_dcm_exdes -file routed.sdf 
-write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clkmgr_dcm_exdes -file routed.v
-report_timing -nworst 30 -path_type full -file routed.twr
-report_drc -file report.drc
-write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit