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diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh b/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh
deleted file mode 100644
index 2c64bee..0000000
--- a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh
+++ /dev/null
@@ -1,91 +0,0 @@
-#!/bin/sh
-# file: implement.sh
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-# Clean up the results directory
-rm -rf results
-mkdir results
-
-# Copy unisim_comp.v file to results directory
-cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
-
-# Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-mv clkmgr_dcm_exdes.ngc results/
-
-#  Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-cp ../example_design/clkmgr_dcm_exdes.ucf results/
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
-
-echo 'Running map'
-map -timing clkmgr_dcm_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
-
-cd ..