diff options
Diffstat (limited to 'common/rtl/ipcore/clkmgr_dcm.xise')
| -rw-r--r-- | common/rtl/ipcore/clkmgr_dcm.xise | 74 |
1 files changed, 0 insertions, 74 deletions
diff --git a/common/rtl/ipcore/clkmgr_dcm.xise b/common/rtl/ipcore/clkmgr_dcm.xise deleted file mode 100644 index 7369d3b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.xise +++ /dev/null @@ -1,74 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no" ?> -<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> - - <header> - <!-- ISE source project file created by Project Navigator. --> - <!-- --> - <!-- This file contains project source information including a list of --> - <!-- project source files, project and process properties. This file, --> - <!-- along with the project source files, is sufficient to open and --> - <!-- implement in ISE Project Navigator. --> - <!-- --> - <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> - </header> - - <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> - - <files> - <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF"> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> - </file> - <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> - <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> - </file> - </files> - - <properties> - <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> - <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> - <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> - <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top" xil_pn:value="Module|clkmgr_dcm" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top File" xil_pn:value="clkmgr_dcm.v" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clkmgr_dcm" xil_pn:valueState="non-default"/> - <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> - <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> - <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> - <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> - <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> - <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> - <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> - <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> - <!-- --> - <!-- The following properties are for internal use only. These should not be modified.--> - <!-- --> - <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-01T08:50:04" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="67BEB73269CA45ADBC7997434CEC13CB" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> - </properties> - - <bindings> - <binding xil_pn:location="/clkmgr_dcm" xil_pn:name="clkmgr_dcm.ucf"/> - </bindings> - - <libraries/> - - <autoManagedFiles> - <!-- The following files are identified by `include statements in verilog --> - <!-- source files and are automatically managed by Project Navigator. --> - <!-- --> - <!-- Do not hand-edit this section, as it will be overwritten when the --> - <!-- project is analyzed based on files automatically identified as --> - <!-- include files. --> - </autoManagedFiles> - -</project> |