1 files changed, 0 insertions, 27 deletions
diff --git a/common/rtl/ipcore/_xmsgs/cg.xmsgs b/common/rtl/ipcore/_xmsgs/cg.xmsgs
deleted file mode 100644
index 985e6e3..0000000
--- a/common/rtl/ipcore/_xmsgs/cg.xmsgs
+++ /dev/null
@@ -1,27 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated
-     by the Xilinx ISE software.  Any direct editing or
-     changes made to this file may result in unpredictable
-     behavior or data corruption.  It is strongly advised that
-     users do not edit the contents of this file. -->
-<messages>
-<msg type="info" file="sim" num="172" delta="old" >Generating IP...
-</msg>
-
-<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;clkmgr_dcm&apos; already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
-
-<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;clkmgr_dcm&apos; already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
-
-<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
-</msg>
-
-<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
-</msg>
-
-<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
-</msg>
-
-</messages>
-