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authorJoachim Strömbergson <joachim@secworks.se>2015-04-01 16:28:03 +0200
committerJoachim Strömbergson <joachim@secworks.se>2015-04-01 16:28:03 +0200
commit38d62bec91558562f738dd4730d7a9dbb3fabf7d (patch)
treee1828d8a5df1fbb020999d0efc8e3b972374c38b /eim/sw/hash_tester_eim.c
parent17d551b2137072a4a724d524091882b73f971336 (diff)
Refactor: Moved all address defines for cryptech cores into a common header file.
Diffstat (limited to 'eim/sw/hash_tester_eim.c')
-rw-r--r--eim/sw/hash_tester_eim.c88
1 files changed, 7 insertions, 81 deletions
diff --git a/eim/sw/hash_tester_eim.c b/eim/sw/hash_tester_eim.c
index e0bcc03..1a37c11 100644
--- a/eim/sw/hash_tester_eim.c
+++ b/eim/sw/hash_tester_eim.c
@@ -1,4 +1,4 @@
-/*
+/*
* hash_tester.c
* --------------
* This program sends several commands to the coretest_hashes subsystem
@@ -11,10 +11,10 @@
* NIST KAT document:
* http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
*
- *
+ *
* Authors: Joachim Strömbergson, Paul Selkirk
* Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
@@ -53,86 +53,12 @@
#include <signal.h>
#include "tc_eim.h"
+#include "cryptech_memory_map.h"
int debug = 0;
int quiet = 0;
int repeat = 0;
-/* memory segments for core families */
-#define SEGMENT_OFFSET_GLOBALS EIM_BASE_ADDR + 0x000000
-#define SEGMENT_OFFSET_HASHES EIM_BASE_ADDR + 0x010000
-#define SEGMENT_OFFSET_RNGS EIM_BASE_ADDR + 0x020000
-#define SEGMENT_OFFSET_CIPHERS EIM_BASE_ADDR + 0x030000
-
-#define CORE_SIZE (0x100 << 2)
-
-/* addresses and codes common to all cores */
-#define ADDR_NAME0 (0x0 << 2)
-#define ADDR_NAME1 (0x1 << 2)
-#define ADDR_VERSION (0x2 << 2)
-
-/* At segment 0, we have board-level register and communication channel registers */
-#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE)
-#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0
-#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1
-#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION
-#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + (0xFF << 2)
-
-#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE)
-#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0
-#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1
-#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION
-
-/* addresses and codes common to all hash cores */
-#define ADDR_CTRL (0x8 << 2)
-#define CTRL_INIT_CMD 1
-#define CTRL_NEXT_CMD 2
-#define ADDR_STATUS (9 << 2)
-#define STATUS_READY_BIT 1
-#define STATUS_VALID_BIT 2
-#define ADDR_BLOCK (0x10 << 2)
-#define ADDR_DIGEST (0x20 << 2)
-
-/* addresses and codes for the specific hash cores */
-#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0*CORE_SIZE)
-#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0
-#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1
-#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION
-#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL
-#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS
-#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK
-#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST
-#define SHA1_BLOCK_LEN 512 / 8
-#define SHA1_DIGEST_LEN 160 / 8
-
-#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1*CORE_SIZE)
-#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0
-#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1
-#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION
-#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL
-#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS
-#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK
-#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST
-#define SHA256_BLOCK_LEN 512 / 8
-#define SHA256_DIGEST_LEN 256 / 8
-
-#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2*CORE_SIZE)
-#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0
-#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1
-#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION
-#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL
-#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS
-#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK
-#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + (0x40 << 2)
-#define SHA512_BLOCK_LEN 1024 / 8
-#define SHA512_224_DIGEST_LEN 224 / 8
-#define SHA512_256_DIGEST_LEN 256 / 8
-#define SHA384_DIGEST_LEN 384 / 8
-#define SHA512_DIGEST_LEN 512 / 8
-#define MODE_SHA_512_224 0 << 2
-#define MODE_SHA_512_256 1 << 2
-#define MODE_SHA_384 2 << 2
-#define MODE_SHA_512 3 << 2
/* SHA-1/SHA-256 One Block Message Sample
Input Message: "abc" */
@@ -274,7 +200,7 @@ const uint8_t NIST_1024_DOUBLE1[] =
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 };
-const uint8_t SHA512_224_DOUBLE_DIGEST[] =
+const uint8_t SHA512_224_DOUBLE_DIGEST[] =
{ 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23,
0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33,
0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72,
@@ -476,7 +402,7 @@ int TC5()
int TC6()
{
const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 };
- static const uint8_t block0_expected[] =
+ static const uint8_t block0_expected[] =
{ 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95,
0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C,
0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11,
@@ -517,7 +443,7 @@ int TC7()
0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f };
/* final digest after 1000 iterations */
- static const uint8_t expected[] =
+ static const uint8_t expected[] =
{ 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6,
0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf,
0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28,