Refactor: Moved all address defines for cryptech cores into a common header file.

5 files changed, 217 insertions, 252 deletions

diff --git a/eim/sw/Makefile b/eim/sw/Makefile
index 8e584fa..263a327 100755
--- a/eim/sw/Makefile
+++ b/eim/sw/Makefile
@@ -6,12 +6,12 @@ all: hash_tester_eim trng_tester_eim hash_eim
 hash_tester_eim: hash_tester_eim.o novena-eim.o tc_eim.o
 	gcc -o $@ $^
 
-hash_tester_eim.o: hash_tester_eim.c tc_eim.h
+hash_tester_eim.o: hash_tester_eim.c tc_eim.h cryptech_memory_map.h
 
 trng_tester_eim: trng_tester_eim.o novena-eim.o tc_eim.o
 	gcc -o $@ $^
 
-trng_tester_eim.o: trng_tester_eim.c tc_eim.h
+trng_tester_eim.o: trng_tester_eim.c tc_eim.h cryptech_memory_map.h
 
 hash_eim: hash_eim.o novena-eim.o tc_eim.o
 	gcc -o $@ $^
diff --git a/eim/sw/cryptech_memory_map.h b/eim/sw/cryptech_memory_map.h
new file mode 100644
index 0000000..c392584
--- /dev/null
+++ b/eim/sw/cryptech_memory_map.h
@@ -0,0 +1,199 @@
+//======================================================================
+//
+// cryptech_memory_map.h
+// ---------------------
+// The memory map for Cryptech cores.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+// Include platform header and define base address based on platform.
+#include "novena-eim.h"
+#define CT_BASE_ADDR EIM_BASE_ADDR
+
+
+// Segments.
+#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
+#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
+#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
+#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
+
+
+// addresses and codes common to all cores
+#define ADDR_NAME0              (0x0 << 2)
+#define ADDR_NAME1              (0x1 << 2)
+#define ADDR_VERSION            (0x2 << 2)
+
+
+//------------------------------------------------------------------
+// Board segment.
+// Board-level registers and communication channel registers
+//------------------------------------------------------------------
+#define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + 0x0000
+#define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
+#define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
+#define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
+#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
+
+#define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + 0x0400
+#define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
+#define COMM_ADDR_NAME1         COMM_ADDR_BASE + ADDR_NAME1
+#define COMM_ADDR_VERSION       COMM_ADDR_BASE + ADDR_VERSION
+
+// addresses and codes common to all hash cores */
+#define ADDR_CTRL               (0x8 << 2)
+#define CTRL_INIT_CMD           1
+#define CTRL_NEXT_CMD           2
+#define ADDR_STATUS             (9 << 2)
+#define STATUS_READY_BIT        1
+#define STATUS_VALID_BIT        2
+#define ADDR_BLOCK              (0x10 << 2)
+#define ADDR_DIGEST             (0x20 << 2)
+
+
+//------------------------------------------------------------------
+// Hashes segment.
+//------------------------------------------------------------------
+#define HASH_CORE_SIZE          (0x100 << 2)
+
+// addresses and codes for the specific hash cores.
+#define SHA1_ADDR_BASE          SEGMENT_OFFSET_HASHES + (0*HASH_CORE_SIZE)
+#define SHA1_ADDR_NAME0         SHA1_ADDR_BASE + ADDR_NAME0
+#define SHA1_ADDR_NAME1         SHA1_ADDR_BASE + ADDR_NAME1
+#define SHA1_ADDR_VERSION       SHA1_ADDR_BASE + ADDR_VERSION
+#define SHA1_ADDR_CTRL          SHA1_ADDR_BASE + ADDR_CTRL
+#define SHA1_ADDR_STATUS        SHA1_ADDR_BASE + ADDR_STATUS
+#define SHA1_ADDR_BLOCK         SHA1_ADDR_BASE + ADDR_BLOCK
+#define SHA1_ADDR_DIGEST        SHA1_ADDR_BASE + ADDR_DIGEST
+#define SHA1_BLOCK_LEN          512 / 8
+#define SHA1_DIGEST_LEN         160 / 8
+
+#define SHA256_ADDR_BASE        SEGMENT_OFFSET_HASHES + (1*HASH_CORE_SIZE)
+#define SHA256_ADDR_NAME0       SHA256_ADDR_BASE + ADDR_NAME0
+#define SHA256_ADDR_NAME1       SHA256_ADDR_BASE + ADDR_NAME1
+#define SHA256_ADDR_VERSION     SHA256_ADDR_BASE + ADDR_VERSION
+#define SHA256_ADDR_CTRL        SHA256_ADDR_BASE + ADDR_CTRL
+#define SHA256_ADDR_STATUS      SHA256_ADDR_BASE + ADDR_STATUS
+#define SHA256_ADDR_BLOCK       SHA256_ADDR_BASE + ADDR_BLOCK
+#define SHA256_ADDR_DIGEST      SHA256_ADDR_BASE + ADDR_DIGEST
+#define SHA256_BLOCK_LEN        512 / 8
+#define SHA256_DIGEST_LEN       256 / 8
+
+#define SHA512_ADDR_BASE        SEGMENT_OFFSET_HASHES + (2*HASH_CORE_SIZE)
+#define SHA512_ADDR_NAME0       SHA512_ADDR_BASE + ADDR_NAME0
+#define SHA512_ADDR_NAME1       SHA512_ADDR_BASE + ADDR_NAME1
+#define SHA512_ADDR_VERSION     SHA512_ADDR_BASE + ADDR_VERSION
+#define SHA512_ADDR_CTRL        SHA512_ADDR_BASE + ADDR_CTRL
+#define SHA512_ADDR_STATUS      SHA512_ADDR_BASE + ADDR_STATUS
+#define SHA512_ADDR_BLOCK       SHA512_ADDR_BASE + ADDR_BLOCK
+#define SHA512_ADDR_DIGEST      SHA512_ADDR_BASE + 0x100
+#define SHA512_BLOCK_LEN        1024 / 8
+#define SHA512_224_DIGEST_LEN   224 / 8
+#define SHA512_256_DIGEST_LEN   256 / 8
+#define SHA384_DIGEST_LEN       384 / 8
+#define SHA512_DIGEST_LEN       512 / 8
+#define MODE_SHA_512_224        0 << 2
+#define MODE_SHA_512_256        1 << 2
+#define MODE_SHA_384            2 << 2
+#define MODE_SHA_512            3 << 2
+
+
+// -----------------------------------------------------------------
+// TRNG segment.
+// -----------------------------------------------------------------
+#define TRNG_CORE_SIZE               (0x100 << 2)
+
+// addresses and codes for the TRNG cores */
+#define TRNG_ADDR_BASE          SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE)
+#define TRNG_ADDR_NAME0         TRNG_ADDR_BASE + ADDR_NAME0
+#define TRNG_ADDR_NAME1         TRNG_ADDR_BASE + ADDR_NAME1
+#define TRNG_ADDR_VERSION       TRNG_ADDR_BASE + ADDR_VERSION
+#define TRNG_ADDR_CTRL          TRNG_ADDR_BASE + (0x10 << 2)
+#define TRNG_CTRL_DISCARD       1
+#define TRNG_CTRL_TEST_MODE     2
+#define TRNG_ADDR_STATUS        TRNG_ADDR_BASE + (0x11 << 2)
+// no status bits defined (yet)
+#define TRNG_ADDR_DELAY         TRNG_ADDR_BASE + (0x13 << 2)
+
+#define ENTROPY1_ADDR_BASE      SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE)
+#define ENTROPY1_ADDR_NAME0     ENTROPY1_ADDR_BASE + ADDR_NAME0
+#define ENTROPY1_ADDR_NAME1     ENTROPY1_ADDR_BASE + ADDR_NAME1
+#define ENTROPY1_ADDR_VERSION   ENTROPY1_ADDR_BASE + ADDR_VERSION
+#define ENTROPY1_ADDR_CTRL      ENTROPY1_ADDR_BASE + (0x10 << 2)
+#define ENTROPY1_CTRL_ENABLE    1
+#define ENTROPY1_ADDR_STATUS    ENTROPY1_ADDR_BASE + (0x11 << 2)
+#define ENTROPY1_STATUS_VALID   1
+#define ENTROPY1_ADDR_ENTROPY   ENTROPY1_ADDR_BASE + (0x20 << 2)
+#define ENTROPY1_ADDR_DELTA     ENTROPY1_ADDR_BASE + (0x30 << 2)
+
+#define ENTROPY2_ADDR_BASE      SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE)
+#define ENTROPY2_ADDR_NAME0     ENTROPY2_ADDR_BASE + ADDR_NAME0
+#define ENTROPY2_ADDR_NAME1     ENTROPY2_ADDR_BASE + ADDR_NAME1
+#define ENTROPY2_ADDR_VERSION   ENTROPY2_ADDR_BASE + ADDR_VERSION
+#define ENTROPY2_ADDR_CTRL      ENTROPY2_ADDR_BASE + (0x10 << 2)
+#define ENTROPY2_CTRL_ENABLE    1
+#define ENTROPY2_ADDR_STATUS    ENTROPY2_ADDR_BASE + (0x11 << 2)
+#define ENTROPY2_STATUS_VALID   1
+#define ENTROPY2_ADDR_OPA       ENTROPY2_ADDR_BASE + (0x18 << 2)
+#define ENTROPY2_ADDR_OPB       ENTROPY2_ADDR_BASE + (0x19 << 2)
+#define ENTROPY2_ADDR_ENTROPY   ENTROPY2_ADDR_BASE + (0x20 << 2)
+#define ENTROPY2_ADDR_RAW       ENTROPY2_ADDR_BASE + (0x21 << 2)
+#define ENTROPY2_ADDR_ROSC      ENTROPY2_ADDR_BASE + (0x22 << 2)
+
+#define MIXER_ADDR_BASE         SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE)
+#define MIXER_ADDR_NAME0        MIXER_ADDR_BASE + ADDR_NAME0
+#define MIXER_ADDR_NAME1        MIXER_ADDR_BASE + ADDR_NAME1
+#define MIXER_ADDR_VERSION      MIXER_ADDR_BASE + ADDR_VERSION
+#define MIXER_ADDR_CTRL         MIXER_ADDR_BASE + (0x10 << 2)
+#define MIXER_CTRL_ENABLE       1
+#define MIXER_CTRL_RESTART      2
+#define MIXER_ADDR_STATUS       MIXER_ADDR_BASE + (0x11 << 2)
+// no status bits defined (yet)
+#define MIXER_ADDR_TIMEOUT      MIXER_ADDR_BASE + (0x20 << 2)
+
+#define CSPRNG_ADDR_BASE        SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE)
+#define CSPRNG_ADDR_NAME0       CSPRNG_ADDR_BASE + ADDR_NAME0
+#define CSPRNG_ADDR_NAME1       CSPRNG_ADDR_BASE + ADDR_NAME1
+#define CSPRNG_ADDR_VERSION     CSPRNG_ADDR_BASE + ADDR_VERSION
+#define CSPRNG_ADDR_CTRL        CSPRNG_ADDR_BASE + (0x10 << 2)
+#define CSPRNG_CTRL_ENABLE      1
+#define CSPRNG_CTRL_SEED        2
+#define CSPRNG_ADDR_STATUS      CSPRNG_ADDR_BASE + (0x11 << 2)
+#define CSPRNG_STATUS_VALID     1
+#define CSPRNG_ADDR_RANDOM      CSPRNG_ADDR_BASE + (0x20 << 2)
+#define CSPRNG_ADDR_NROUNDS     CSPRNG_ADDR_BASE + (0x40 << 2)
+#define CSPRNG_ADDR_NBLOCKS_LO  CSPRNG_ADDR_BASE + (0x41 << 2)
+#define CSPRNG_ADDR_NBLOCKS_HI  CSPRNG_ADDR_BASE + (0x42 << 2)
+
+//======================================================================
+// EOF cryptech_memory_map.h
+//======================================================================
diff --git a/eim/sw/hash_eim.c b/eim/sw/hash_eim.c
index 281914c..8ea761b 100644
--- a/eim/sw/hash_eim.c
+++ b/eim/sw/hash_eim.c
@@ -1,13 +1,13 @@
-/* 
+/*
  * hash.c
  * ------
  * This program uses the coretest_hashes subsystem to produce a
  * cryptographic hash of a file or input stream. It is a generalization
  * of the hash_tester.c test program.
- * 
+ *
  * Authors: Joachim Strömbergson, Paul Selkirk
  * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met:
@@ -51,8 +51,9 @@
 #include <assert.h>
 
 #include "tc_eim.h"
+#include "cryptech_memory_map.h"
 
-char *usage = 
+char *usage =
 "Usage: %s [-d] [-v] [-q] [algorithm [file]]\n"
 "algorithms: sha-1, sha-256, sha-512/224, sha-512/256, sha-384, sha-512\n";
 
@@ -60,81 +61,6 @@ int debug = 0;
 int quiet = 0;
 int verbose = 0;
 
-/* memory segments for core families */
-#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
-#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
-#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
-#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
-
-#define CORE_SIZE               (0x100 << 2)
-
-/* addresses and codes common to all cores */
-#define ADDR_NAME0              (0x0 << 2)
-#define ADDR_NAME1              (0x1 << 2)
-#define ADDR_VERSION            (0x2 << 2)
-
-/* At segment 0, we have board-level register and communication channel registers */
-#define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE)
-#define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
-#define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
-#define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
-#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
-
-#define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE)
-#define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
-#define COMM_ADDR_NAME1         COMM_ADDR_BASE + ADDR_NAME1
-#define COMM_ADDR_VERSION       COMM_ADDR_BASE + ADDR_VERSION
-
-/* addresses and codes common to all hash cores */
-#define ADDR_CTRL               (0x8 << 2)
-#define CTRL_INIT_CMD           1
-#define CTRL_NEXT_CMD           2
-#define ADDR_STATUS             (9 << 2)
-#define STATUS_READY_BIT        1
-#define STATUS_VALID_BIT        2
-#define ADDR_BLOCK              (0x10 << 2)
-#define ADDR_DIGEST             (0x20 << 2)
-
-/* addresses and codes for the specific hash cores */
-#define SHA1_ADDR_BASE          SEGMENT_OFFSET_HASHES + (0*CORE_SIZE)
-#define SHA1_ADDR_NAME0         SHA1_ADDR_BASE + ADDR_NAME0
-#define SHA1_ADDR_NAME1         SHA1_ADDR_BASE + ADDR_NAME1
-#define SHA1_ADDR_VERSION       SHA1_ADDR_BASE + ADDR_VERSION
-#define SHA1_ADDR_CTRL          SHA1_ADDR_BASE + ADDR_CTRL
-#define SHA1_ADDR_STATUS        SHA1_ADDR_BASE + ADDR_STATUS
-#define SHA1_ADDR_BLOCK         SHA1_ADDR_BASE + ADDR_BLOCK
-#define SHA1_ADDR_DIGEST        SHA1_ADDR_BASE + ADDR_DIGEST
-#define SHA1_BLOCK_LEN          512 / 8
-#define SHA1_DIGEST_LEN         160 / 8
-
-#define SHA256_ADDR_BASE        SEGMENT_OFFSET_HASHES + (1*CORE_SIZE)
-#define SHA256_ADDR_NAME0       SHA256_ADDR_BASE + ADDR_NAME0
-#define SHA256_ADDR_NAME1       SHA256_ADDR_BASE + ADDR_NAME1
-#define SHA256_ADDR_VERSION     SHA256_ADDR_BASE + ADDR_VERSION
-#define SHA256_ADDR_CTRL        SHA256_ADDR_BASE + ADDR_CTRL
-#define SHA256_ADDR_STATUS      SHA256_ADDR_BASE + ADDR_STATUS
-#define SHA256_ADDR_BLOCK       SHA256_ADDR_BASE + ADDR_BLOCK
-#define SHA256_ADDR_DIGEST      SHA256_ADDR_BASE + ADDR_DIGEST
-#define SHA256_BLOCK_LEN        512 / 8
-#define SHA256_DIGEST_LEN       256 / 8
-
-#define SHA512_ADDR_BASE        SEGMENT_OFFSET_HASHES + (2*CORE_SIZE)
-#define SHA512_ADDR_NAME0       SHA512_ADDR_BASE + ADDR_NAME0
-#define SHA512_ADDR_NAME1       SHA512_ADDR_BASE + ADDR_NAME1
-#define SHA512_ADDR_VERSION     SHA512_ADDR_BASE + ADDR_VERSION
-#define SHA512_ADDR_CTRL        SHA512_ADDR_BASE + ADDR_CTRL
-#define SHA512_ADDR_STATUS      SHA512_ADDR_BASE + ADDR_STATUS
-#define SHA512_ADDR_BLOCK       SHA512_ADDR_BASE + ADDR_BLOCK
-#define SHA512_ADDR_DIGEST      SHA512_ADDR_BASE + (0x40 << 2)
-#define SHA512_BLOCK_LEN        1024 / 8
-#define SHA512_224_DIGEST_LEN   224 / 8
-#define SHA512_256_DIGEST_LEN   256 / 8
-#define SHA384_DIGEST_LEN       384 / 8
-#define SHA512_DIGEST_LEN       512 / 8
-#define MODE_SHA_512_224        0 << 2
-#define MODE_SHA_512_256        1 << 2
-#define MODE_SHA_384            2 << 2
-#define MODE_SHA_512            3 << 2
 
 /* ---------------- algorithm lookup code ---------------- */
 
diff --git a/eim/sw/hash_tester_eim.c b/eim/sw/hash_tester_eim.c
index e0bcc03..1a37c11 100644
--- a/eim/sw/hash_tester_eim.c
+++ b/eim/sw/hash_tester_eim.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * hash_tester.c
  * --------------
  * This program sends several commands to the coretest_hashes subsystem
@@ -11,10 +11,10 @@
  * NIST KAT document:
  * http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
  *
- * 
+ *
  * Authors: Joachim Strömbergson, Paul Selkirk
  * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met:
@@ -53,86 +53,12 @@
 #include <signal.h>
 
 #include "tc_eim.h"
+#include "cryptech_memory_map.h"
 
 int debug = 0;
 int quiet = 0;
 int repeat = 0;
 
-/* memory segments for core families */
-#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
-#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
-#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
-#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
-
-#define CORE_SIZE               (0x100 << 2)
-
-/* addresses and codes common to all cores */
-#define ADDR_NAME0              (0x0 << 2)
-#define ADDR_NAME1              (0x1 << 2)
-#define ADDR_VERSION            (0x2 << 2)
-
-/* At segment 0, we have board-level register and communication channel registers */
-#define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE)
-#define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
-#define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
-#define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
-#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
-
-#define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE)
-#define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
-#define COMM_ADDR_NAME1         COMM_ADDR_BASE + ADDR_NAME1
-#define COMM_ADDR_VERSION       COMM_ADDR_BASE + ADDR_VERSION
-
-/* addresses and codes common to all hash cores */
-#define ADDR_CTRL               (0x8 << 2)
-#define CTRL_INIT_CMD           1
-#define CTRL_NEXT_CMD           2
-#define ADDR_STATUS             (9 << 2)
-#define STATUS_READY_BIT        1
-#define STATUS_VALID_BIT        2
-#define ADDR_BLOCK              (0x10 << 2)
-#define ADDR_DIGEST             (0x20 << 2)
-
-/* addresses and codes for the specific hash cores */
-#define SHA1_ADDR_BASE          SEGMENT_OFFSET_HASHES + (0*CORE_SIZE)
-#define SHA1_ADDR_NAME0         SHA1_ADDR_BASE + ADDR_NAME0
-#define SHA1_ADDR_NAME1         SHA1_ADDR_BASE + ADDR_NAME1
-#define SHA1_ADDR_VERSION       SHA1_ADDR_BASE + ADDR_VERSION
-#define SHA1_ADDR_CTRL          SHA1_ADDR_BASE + ADDR_CTRL
-#define SHA1_ADDR_STATUS        SHA1_ADDR_BASE + ADDR_STATUS
-#define SHA1_ADDR_BLOCK         SHA1_ADDR_BASE + ADDR_BLOCK
-#define SHA1_ADDR_DIGEST        SHA1_ADDR_BASE + ADDR_DIGEST
-#define SHA1_BLOCK_LEN          512 / 8
-#define SHA1_DIGEST_LEN         160 / 8
-
-#define SHA256_ADDR_BASE        SEGMENT_OFFSET_HASHES + (1*CORE_SIZE)
-#define SHA256_ADDR_NAME0       SHA256_ADDR_BASE + ADDR_NAME0
-#define SHA256_ADDR_NAME1       SHA256_ADDR_BASE + ADDR_NAME1
-#define SHA256_ADDR_VERSION     SHA256_ADDR_BASE + ADDR_VERSION
-#define SHA256_ADDR_CTRL        SHA256_ADDR_BASE + ADDR_CTRL
-#define SHA256_ADDR_STATUS      SHA256_ADDR_BASE + ADDR_STATUS
-#define SHA256_ADDR_BLOCK       SHA256_ADDR_BASE + ADDR_BLOCK
-#define SHA256_ADDR_DIGEST      SHA256_ADDR_BASE + ADDR_DIGEST
-#define SHA256_BLOCK_LEN        512 / 8
-#define SHA256_DIGEST_LEN       256 / 8
-
-#define SHA512_ADDR_BASE        SEGMENT_OFFSET_HASHES + (2*CORE_SIZE)
-#define SHA512_ADDR_NAME0       SHA512_ADDR_BASE + ADDR_NAME0
-#define SHA512_ADDR_NAME1       SHA512_ADDR_BASE + ADDR_NAME1
-#define SHA512_ADDR_VERSION     SHA512_ADDR_BASE + ADDR_VERSION
-#define SHA512_ADDR_CTRL        SHA512_ADDR_BASE + ADDR_CTRL
-#define SHA512_ADDR_STATUS      SHA512_ADDR_BASE + ADDR_STATUS
-#define SHA512_ADDR_BLOCK       SHA512_ADDR_BASE + ADDR_BLOCK
-#define SHA512_ADDR_DIGEST      SHA512_ADDR_BASE + (0x40 << 2)
-#define SHA512_BLOCK_LEN        1024 / 8
-#define SHA512_224_DIGEST_LEN   224 / 8
-#define SHA512_256_DIGEST_LEN   256 / 8
-#define SHA384_DIGEST_LEN       384 / 8
-#define SHA512_DIGEST_LEN       512 / 8
-#define MODE_SHA_512_224        0 << 2
-#define MODE_SHA_512_256        1 << 2
-#define MODE_SHA_384            2 << 2
-#define MODE_SHA_512            3 << 2
 
 /* SHA-1/SHA-256 One Block Message Sample
    Input Message: "abc" */
@@ -274,7 +200,7 @@ const uint8_t NIST_1024_DOUBLE1[] =
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 };
 
-const uint8_t SHA512_224_DOUBLE_DIGEST[] = 
+const uint8_t SHA512_224_DOUBLE_DIGEST[] =
 { 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23,
   0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33,
   0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72,
@@ -476,7 +402,7 @@ int TC5()
 int TC6()
 {
     const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 };
-    static const uint8_t block0_expected[] = 
+    static const uint8_t block0_expected[] =
         { 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95,
           0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C,
           0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11,
@@ -517,7 +443,7 @@ int TC7()
           0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f };
 
     /* final digest after 1000 iterations */
-    static const uint8_t expected[] = 
+    static const uint8_t expected[] =
         { 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6,
           0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf,
           0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28,
diff --git a/eim/sw/trng_tester_eim.c b/eim/sw/trng_tester_eim.c
index eb30045..f60aeec 100644
--- a/eim/sw/trng_tester_eim.c
+++ b/eim/sw/trng_tester_eim.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * trng_tester.c
  * --------------
  * This program sends several commands to the TRNG subsystem
@@ -6,10 +6,10 @@
  *
  * Note: This version of the program talks to the FPGA over an EIM bus.
  *
- * 
+ *
  * Author: Paul Selkirk
  * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met:
@@ -48,6 +48,7 @@
 #include <signal.h>
 
 #include "tc_eim.h"
+#include "cryptech_memory_map.h"
 
 #define WAIT_STATS      /* report number of status reads before core says "ready" */
 
@@ -56,93 +57,6 @@ int quiet = 0;
 int repeat = 0;
 int num_words = 10;
 
-/* memory segments for core families */
-#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
-#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
-#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
-#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
-
-#define CORE_SIZE               (0x100 << 2)
-
-/* addresses and codes common to all cores */
-#define ADDR_NAME0              (0x0 << 2)
-#define ADDR_NAME1              (0x1 << 2)
-#define ADDR_VERSION            (0x2 << 2)
-
-/* At segment 0, we have board-level register and communication channel registers */
-#define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE)
-#define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
-#define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
-#define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
-#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
-
-#define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE)
-#define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
-#define COMM_ADDR_NAME1         COMM_ADDR_BASE + ADDR_NAME1
-#define COMM_ADDR_VERSION       COMM_ADDR_BASE + ADDR_VERSION
-
-/* addresses and codes for the TRNG cores */
-#define TRNG_ADDR_BASE          SEGMENT_OFFSET_RNGS + (0x00 * CORE_SIZE)
-#define TRNG_ADDR_NAME0         TRNG_ADDR_BASE + ADDR_NAME0
-#define TRNG_ADDR_NAME1         TRNG_ADDR_BASE + ADDR_NAME1
-#define TRNG_ADDR_VERSION       TRNG_ADDR_BASE + ADDR_VERSION
-#define TRNG_ADDR_CTRL          TRNG_ADDR_BASE + (0x10 << 2)
-#define TRNG_CTRL_DISCARD       1
-#define TRNG_CTRL_TEST_MODE     2
-#define TRNG_ADDR_STATUS        TRNG_ADDR_BASE + (0x11 << 2)
-/* no status bits defined */
-#define TRNG_ADDR_DELAY         TRNG_ADDR_BASE + (0x13 << 2)
-
-#define ENTROPY1_ADDR_BASE      SEGMENT_OFFSET_RNGS + (0x05 * CORE_SIZE)
-#define ENTROPY1_ADDR_NAME0     ENTROPY1_ADDR_BASE + ADDR_NAME0
-#define ENTROPY1_ADDR_NAME1     ENTROPY1_ADDR_BASE + ADDR_NAME1
-#define ENTROPY1_ADDR_VERSION   ENTROPY1_ADDR_BASE + ADDR_VERSION
-#define ENTROPY1_ADDR_CTRL      ENTROPY1_ADDR_BASE + (0x10 << 2)
-#define ENTROPY1_CTRL_ENABLE    1
-#define ENTROPY1_ADDR_STATUS    ENTROPY1_ADDR_BASE + (0x11 << 2)
-#define ENTROPY1_STATUS_VALID   1
-#define ENTROPY1_ADDR_ENTROPY   ENTROPY1_ADDR_BASE + (0x20 << 2)
-#define ENTROPY1_ADDR_DELTA     ENTROPY1_ADDR_BASE + (0x30 << 2)
-
-#define ENTROPY2_ADDR_BASE      SEGMENT_OFFSET_RNGS + (0x06 * CORE_SIZE)
-#define ENTROPY2_ADDR_NAME0     ENTROPY2_ADDR_BASE + ADDR_NAME0
-#define ENTROPY2_ADDR_NAME1     ENTROPY2_ADDR_BASE + ADDR_NAME1
-#define ENTROPY2_ADDR_VERSION   ENTROPY2_ADDR_BASE + ADDR_VERSION
-#define ENTROPY2_ADDR_CTRL      ENTROPY2_ADDR_BASE + (0x10 << 2)
-#define ENTROPY2_CTRL_ENABLE    1
-#define ENTROPY2_ADDR_STATUS    ENTROPY2_ADDR_BASE + (0x11 << 2)
-#define ENTROPY2_STATUS_VALID   1
-#define ENTROPY2_ADDR_OPA       ENTROPY2_ADDR_BASE + (0x18 << 2)
-#define ENTROPY2_ADDR_OPB       ENTROPY2_ADDR_BASE + (0x19 << 2)
-#define ENTROPY2_ADDR_ENTROPY   ENTROPY2_ADDR_BASE + (0x20 << 2)
-#define ENTROPY2_ADDR_RAW       ENTROPY2_ADDR_BASE + (0x21 << 2)
-#define ENTROPY2_ADDR_ROSC      ENTROPY2_ADDR_BASE + (0x22 << 2)
-
-#define MIXER_ADDR_BASE         SEGMENT_OFFSET_RNGS + (0x0a * CORE_SIZE)
-#define MIXER_ADDR_NAME0        MIXER_ADDR_BASE + ADDR_NAME0
-#define MIXER_ADDR_NAME1        MIXER_ADDR_BASE + ADDR_NAME1
-#define MIXER_ADDR_VERSION      MIXER_ADDR_BASE + ADDR_VERSION
-#define MIXER_ADDR_CTRL         MIXER_ADDR_BASE + (0x10 << 2)
-#define MIXER_CTRL_ENABLE       1
-#define MIXER_CTRL_RESTART      2
-#define MIXER_ADDR_STATUS       MIXER_ADDR_BASE + (0x11 << 2)
-/* no status bits defined */
-#define MIXER_ADDR_TIMEOUT      MIXER_ADDR_BASE + (0x20 << 2)
-
-#define CSPRNG_ADDR_BASE        SEGMENT_OFFSET_RNGS + (0x0b * CORE_SIZE)
-#define CSPRNG_ADDR_NAME0       CSPRNG_ADDR_BASE + ADDR_NAME0
-#define CSPRNG_ADDR_NAME1       CSPRNG_ADDR_BASE + ADDR_NAME1
-#define CSPRNG_ADDR_VERSION     CSPRNG_ADDR_BASE + ADDR_VERSION
-#define CSPRNG_ADDR_CTRL        CSPRNG_ADDR_BASE + (0x10 << 2)
-#define CSPRNG_CTRL_ENABLE      1
-#define CSPRNG_CTRL_SEED        2
-#define CSPRNG_ADDR_STATUS      CSPRNG_ADDR_BASE + (0x11 << 2)
-#define CSPRNG_STATUS_VALID     1
-#define CSPRNG_ADDR_RANDOM      CSPRNG_ADDR_BASE + (0x20 << 2)
-#define CSPRNG_ADDR_NROUNDS     CSPRNG_ADDR_BASE + (0x40 << 2)
-#define CSPRNG_ADDR_NBLOCKS_LO  CSPRNG_ADDR_BASE + (0x41 << 2)
-#define CSPRNG_ADDR_NBLOCKS_HI  CSPRNG_ADDR_BASE + (0x42 << 2)
-
 /* ---------------- sanity test case ---------------- */
 
 int TC0()