Refactor: Moved all address defines for cryptech cores into a common header file.

1 files changed, 199 insertions, 0 deletions

diff --git a/eim/sw/cryptech_memory_map.h b/eim/sw/cryptech_memory_map.h
new file mode 100644
index 0000000..c392584
--- /dev/null
+++ b/eim/sw/cryptech_memory_map.h
@@ -0,0 +1,199 @@
+//======================================================================
+//
+// cryptech_memory_map.h
+// ---------------------
+// The memory map for Cryptech cores.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+// Include platform header and define base address based on platform.
+#include "novena-eim.h"
+#define CT_BASE_ADDR EIM_BASE_ADDR
+
+
+// Segments.
+#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
+#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
+#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
+#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
+
+
+// addresses and codes common to all cores
+#define ADDR_NAME0              (0x0 << 2)
+#define ADDR_NAME1              (0x1 << 2)
+#define ADDR_VERSION            (0x2 << 2)
+
+
+//------------------------------------------------------------------
+// Board segment.
+// Board-level registers and communication channel registers
+//------------------------------------------------------------------
+#define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + 0x0000
+#define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
+#define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
+#define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
+#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
+
+#define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + 0x0400
+#define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
+#define COMM_ADDR_NAME1         COMM_ADDR_BASE + ADDR_NAME1
+#define COMM_ADDR_VERSION       COMM_ADDR_BASE + ADDR_VERSION
+
+// addresses and codes common to all hash cores */
+#define ADDR_CTRL               (0x8 << 2)
+#define CTRL_INIT_CMD           1
+#define CTRL_NEXT_CMD           2
+#define ADDR_STATUS             (9 << 2)
+#define STATUS_READY_BIT        1
+#define STATUS_VALID_BIT        2
+#define ADDR_BLOCK              (0x10 << 2)
+#define ADDR_DIGEST             (0x20 << 2)
+
+
+//------------------------------------------------------------------
+// Hashes segment.
+//------------------------------------------------------------------
+#define HASH_CORE_SIZE          (0x100 << 2)
+
+// addresses and codes for the specific hash cores.
+#define SHA1_ADDR_BASE          SEGMENT_OFFSET_HASHES + (0*HASH_CORE_SIZE)
+#define SHA1_ADDR_NAME0         SHA1_ADDR_BASE + ADDR_NAME0
+#define SHA1_ADDR_NAME1         SHA1_ADDR_BASE + ADDR_NAME1
+#define SHA1_ADDR_VERSION       SHA1_ADDR_BASE + ADDR_VERSION
+#define SHA1_ADDR_CTRL          SHA1_ADDR_BASE + ADDR_CTRL
+#define SHA1_ADDR_STATUS        SHA1_ADDR_BASE + ADDR_STATUS
+#define SHA1_ADDR_BLOCK         SHA1_ADDR_BASE + ADDR_BLOCK
+#define SHA1_ADDR_DIGEST        SHA1_ADDR_BASE + ADDR_DIGEST
+#define SHA1_BLOCK_LEN          512 / 8
+#define SHA1_DIGEST_LEN         160 / 8
+
+#define SHA256_ADDR_BASE        SEGMENT_OFFSET_HASHES + (1*HASH_CORE_SIZE)
+#define SHA256_ADDR_NAME0       SHA256_ADDR_BASE + ADDR_NAME0
+#define SHA256_ADDR_NAME1       SHA256_ADDR_BASE + ADDR_NAME1
+#define SHA256_ADDR_VERSION     SHA256_ADDR_BASE + ADDR_VERSION
+#define SHA256_ADDR_CTRL        SHA256_ADDR_BASE + ADDR_CTRL
+#define SHA256_ADDR_STATUS      SHA256_ADDR_BASE + ADDR_STATUS
+#define SHA256_ADDR_BLOCK       SHA256_ADDR_BASE + ADDR_BLOCK
+#define SHA256_ADDR_DIGEST      SHA256_ADDR_BASE + ADDR_DIGEST
+#define SHA256_BLOCK_LEN        512 / 8
+#define SHA256_DIGEST_LEN       256 / 8
+
+#define SHA512_ADDR_BASE        SEGMENT_OFFSET_HASHES + (2*HASH_CORE_SIZE)
+#define SHA512_ADDR_NAME0       SHA512_ADDR_BASE + ADDR_NAME0
+#define SHA512_ADDR_NAME1       SHA512_ADDR_BASE + ADDR_NAME1
+#define SHA512_ADDR_VERSION     SHA512_ADDR_BASE + ADDR_VERSION
+#define SHA512_ADDR_CTRL        SHA512_ADDR_BASE + ADDR_CTRL
+#define SHA512_ADDR_STATUS      SHA512_ADDR_BASE + ADDR_STATUS
+#define SHA512_ADDR_BLOCK       SHA512_ADDR_BASE + ADDR_BLOCK
+#define SHA512_ADDR_DIGEST      SHA512_ADDR_BASE + 0x100
+#define SHA512_BLOCK_LEN        1024 / 8
+#define SHA512_224_DIGEST_LEN   224 / 8
+#define SHA512_256_DIGEST_LEN   256 / 8
+#define SHA384_DIGEST_LEN       384 / 8
+#define SHA512_DIGEST_LEN       512 / 8
+#define MODE_SHA_512_224        0 << 2
+#define MODE_SHA_512_256        1 << 2
+#define MODE_SHA_384            2 << 2
+#define MODE_SHA_512            3 << 2
+
+
+// -----------------------------------------------------------------
+// TRNG segment.
+// -----------------------------------------------------------------
+#define TRNG_CORE_SIZE               (0x100 << 2)
+
+// addresses and codes for the TRNG cores */
+#define TRNG_ADDR_BASE          SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE)
+#define TRNG_ADDR_NAME0         TRNG_ADDR_BASE + ADDR_NAME0
+#define TRNG_ADDR_NAME1         TRNG_ADDR_BASE + ADDR_NAME1
+#define TRNG_ADDR_VERSION       TRNG_ADDR_BASE + ADDR_VERSION
+#define TRNG_ADDR_CTRL          TRNG_ADDR_BASE + (0x10 << 2)
+#define TRNG_CTRL_DISCARD       1
+#define TRNG_CTRL_TEST_MODE     2
+#define TRNG_ADDR_STATUS        TRNG_ADDR_BASE + (0x11 << 2)
+// no status bits defined (yet)
+#define TRNG_ADDR_DELAY         TRNG_ADDR_BASE + (0x13 << 2)
+
+#define ENTROPY1_ADDR_BASE      SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE)
+#define ENTROPY1_ADDR_NAME0     ENTROPY1_ADDR_BASE + ADDR_NAME0
+#define ENTROPY1_ADDR_NAME1     ENTROPY1_ADDR_BASE + ADDR_NAME1
+#define ENTROPY1_ADDR_VERSION   ENTROPY1_ADDR_BASE + ADDR_VERSION
+#define ENTROPY1_ADDR_CTRL      ENTROPY1_ADDR_BASE + (0x10 << 2)
+#define ENTROPY1_CTRL_ENABLE    1
+#define ENTROPY1_ADDR_STATUS    ENTROPY1_ADDR_BASE + (0x11 << 2)
+#define ENTROPY1_STATUS_VALID   1
+#define ENTROPY1_ADDR_ENTROPY   ENTROPY1_ADDR_BASE + (0x20 << 2)
+#define ENTROPY1_ADDR_DELTA     ENTROPY1_ADDR_BASE + (0x30 << 2)
+
+#define ENTROPY2_ADDR_BASE      SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE)
+#define ENTROPY2_ADDR_NAME0     ENTROPY2_ADDR_BASE + ADDR_NAME0
+#define ENTROPY2_ADDR_NAME1     ENTROPY2_ADDR_BASE + ADDR_NAME1
+#define ENTROPY2_ADDR_VERSION   ENTROPY2_ADDR_BASE + ADDR_VERSION
+#define ENTROPY2_ADDR_CTRL      ENTROPY2_ADDR_BASE + (0x10 << 2)
+#define ENTROPY2_CTRL_ENABLE    1
+#define ENTROPY2_ADDR_STATUS    ENTROPY2_ADDR_BASE + (0x11 << 2)
+#define ENTROPY2_STATUS_VALID   1
+#define ENTROPY2_ADDR_OPA       ENTROPY2_ADDR_BASE + (0x18 << 2)
+#define ENTROPY2_ADDR_OPB       ENTROPY2_ADDR_BASE + (0x19 << 2)
+#define ENTROPY2_ADDR_ENTROPY   ENTROPY2_ADDR_BASE + (0x20 << 2)
+#define ENTROPY2_ADDR_RAW       ENTROPY2_ADDR_BASE + (0x21 << 2)
+#define ENTROPY2_ADDR_ROSC      ENTROPY2_ADDR_BASE + (0x22 << 2)
+
+#define MIXER_ADDR_BASE         SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE)
+#define MIXER_ADDR_NAME0        MIXER_ADDR_BASE + ADDR_NAME0
+#define MIXER_ADDR_NAME1        MIXER_ADDR_BASE + ADDR_NAME1
+#define MIXER_ADDR_VERSION      MIXER_ADDR_BASE + ADDR_VERSION
+#define MIXER_ADDR_CTRL         MIXER_ADDR_BASE + (0x10 << 2)
+#define MIXER_CTRL_ENABLE       1
+#define MIXER_CTRL_RESTART      2
+#define MIXER_ADDR_STATUS       MIXER_ADDR_BASE + (0x11 << 2)
+// no status bits defined (yet)
+#define MIXER_ADDR_TIMEOUT      MIXER_ADDR_BASE + (0x20 << 2)
+
+#define CSPRNG_ADDR_BASE        SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE)
+#define CSPRNG_ADDR_NAME0       CSPRNG_ADDR_BASE + ADDR_NAME0
+#define CSPRNG_ADDR_NAME1       CSPRNG_ADDR_BASE + ADDR_NAME1
+#define CSPRNG_ADDR_VERSION     CSPRNG_ADDR_BASE + ADDR_VERSION
+#define CSPRNG_ADDR_CTRL        CSPRNG_ADDR_BASE + (0x10 << 2)
+#define CSPRNG_CTRL_ENABLE      1
+#define CSPRNG_CTRL_SEED        2
+#define CSPRNG_ADDR_STATUS      CSPRNG_ADDR_BASE + (0x11 << 2)
+#define CSPRNG_STATUS_VALID     1
+#define CSPRNG_ADDR_RANDOM      CSPRNG_ADDR_BASE + (0x20 << 2)
+#define CSPRNG_ADDR_NROUNDS     CSPRNG_ADDR_BASE + (0x40 << 2)
+#define CSPRNG_ADDR_NBLOCKS_LO  CSPRNG_ADDR_BASE + (0x41 << 2)
+#define CSPRNG_ADDR_NBLOCKS_HI  CSPRNG_ADDR_BASE + (0x42 << 2)
+
+//======================================================================
+// EOF cryptech_memory_map.h
+//======================================================================