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| author | Rob Austein <sra@hactrn.net> | 2015-09-25 18:57:21 -0400 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2015-09-25 18:57:21 -0400 |
| commit | f43b493bcc7dfe1d6b49faad6dc32c8948573e29 (patch) | |
| tree | be48e40e529ec0e2cedd97c6cdf1610ae560c208 /eim/build/Makefile | |
| parent | d3a2b477d0411b006b7f16256d0b2765ea765a83 (diff) | |
Previous commit was incomplete.
Diffstat (limited to 'eim/build/Makefile')
| -rw-r--r-- | eim/build/Makefile | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/eim/build/Makefile b/eim/build/Makefile index 00d8604..630faa9 100644 --- a/eim/build/Makefile +++ b/eim/build/Makefile @@ -21,22 +21,22 @@ ucf = ../ucf/$(project).ucf # Verilog files that always go with builds on this platform. vfiles = \ - $(core_tree)/platform/novena/eim/rtl/novena_eim.v \ - $(core_tree)/platform/novena/common/rtl/novena_regs.v \ - $(core_tree)/platform/novena/common/rtl/novena_clkmgr.v \ - $(core_tree)/platform/novena/common/rtl/ipcore/clkmgr_dcm.v \ - $(core_tree)/platform/novena/config/core_selector.v \ - $(core_tree)/comm/eim/src/rtl/cdc_bus_pulse.v \ - $(core_tree)/comm/eim/src/rtl/eim_arbiter_cdc.v \ - $(core_tree)/comm/eim/src/rtl/eim_arbiter.v \ - $(core_tree)/comm/eim/src/rtl/eim_da_phy.v \ - $(core_tree)/comm/eim/src/rtl/eim_indicator.v \ - $(core_tree)/comm/eim/src/rtl/eim_regs.v \ - $(core_tree)/comm/eim/src/rtl/eim.v + $(CORE_TREE)/platform/novena/eim/rtl/novena_eim.v \ + $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \ + $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \ + $(CORE_TREE)/platform/novena/common/rtl/ipcore/clkmgr_dcm.v \ + $(CORE_TREE)/platform/novena/config/core_selector.v \ + $(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \ + $(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \ + $(CORE_TREE)/comm/eim/src/rtl/eim_arbiter.v \ + $(CORE_TREE)/comm/eim/src/rtl/eim_da_phy.v \ + $(CORE_TREE)/comm/eim/src/rtl/eim_indicator.v \ + $(CORE_TREE)/comm/eim/src/rtl/eim_regs.v \ + $(CORE_TREE)/comm/eim/src/rtl/eim.v # Verilog files selected by the core configuration script. -include $(core_tree)/platform/novena/config/core_vfiles.mk +-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk include xilinx.mk @@ -45,4 +45,4 @@ include xilinx.mk VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME lint: - verilator ${VERILATOR_FLAGS} $(vfiles) $(core_tree)/platform/novena/common/rtl/lint-dummy.v + verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v |