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# Localize all the relative path awfulness in one variable.

CORE_TREE	:= $(abspath ../../../..)

# Figure out what the native word size is on the build host, because
# the XiLinx tools care for some reason.

WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')

# Parameters to xilinkx.mk.

project		= novena_eim
vendor		= xilinx
family		= spartan6
part		= xc6slx45csg324-3
top_module	= novena_top
isedir		= /opt/Xilinx/14.7/ISE_DS
xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
ucf		= ../ucf/$(project).ucf

# Verilog files that always go with builds on this platform.

vfiles = \
	$(core_tree)/platform/novena/eim/rtl/novena_eim.v \
	$(core_tree)/platform/novena/common/rtl/novena_regs.v \
	$(core_tree)/platform/novena/common/rtl/novena_clkmgr.v \
	$(core_tree)/platform/novena/common/rtl/ipcore/clkmgr_dcm.v \
	$(core_tree)/platform/novena/config/core_selector.v \
	$(core_tree)/comm/eim/src/rtl/cdc_bus_pulse.v \
	$(core_tree)/comm/eim/src/rtl/eim_arbiter_cdc.v \
	$(core_tree)/comm/eim/src/rtl/eim_arbiter.v \
	$(core_tree)/comm/eim/src/rtl/eim_da_phy.v \
	$(core_tree)/comm/eim/src/rtl/eim_indicator.v \
	$(core_tree)/comm/eim/src/rtl/eim_regs.v \
	$(core_tree)/comm/eim/src/rtl/eim.v

# Verilog files selected by the core configuration script.

include $(core_tree)/platform/novena/config/core_vfiles.mk

include xilinx.mk

# Fun extras for running verlator as a linter.

VERILATOR_FLAGS	= --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME

lint:
	verilator ${VERILATOR_FLAGS} $(vfiles) $(core_tree)/platform/novena/common/rtl/lint-dummy.v