diff options
author | Paul Selkirk <pselkirk@isc.org> | 2015-03-17 13:49:30 +0100 |
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committer | Paul Selkirk <pselkirk@isc.org> | 2015-03-17 13:49:30 +0100 |
commit | 283bfbeeb7fb5767815c10ea98bb155638d4bfb3 (patch) | |
tree | 5929001d84e6ef964d1338c71b27418ad8a146bf /common/rtl/ipcore/_xmsgs/cg.xmsgs | |
parent | 21ef7967486b349d66703c13edfff58d5f13372a (diff) |
Rearrange cores.
Diffstat (limited to 'common/rtl/ipcore/_xmsgs/cg.xmsgs')
-rw-r--r-- | common/rtl/ipcore/_xmsgs/cg.xmsgs | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/common/rtl/ipcore/_xmsgs/cg.xmsgs b/common/rtl/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..985e6e3 --- /dev/null +++ b/common/rtl/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
+</msg>
+ +<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+ +<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+ +</messages> +
|