From 283bfbeeb7fb5767815c10ea98bb155638d4bfb3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 17 Mar 2015 13:49:30 +0100 Subject: Rearrange cores. --- common/rtl/ipcore/_xmsgs/cg.xmsgs | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 common/rtl/ipcore/_xmsgs/cg.xmsgs (limited to 'common/rtl/ipcore/_xmsgs/cg.xmsgs') diff --git a/common/rtl/ipcore/_xmsgs/cg.xmsgs b/common/rtl/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..985e6e3 --- /dev/null +++ b/common/rtl/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,27 @@ + + + +Generating IP... + + +A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten. + + +A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten. + + +Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + -- cgit v1.2.3