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Due to security reasons, we must use async reset for sensitive parts of the
design. In short, if the system clock is stopped, which is definitely an
abnormal situation, sync reset won't let us to wipe secret information and a
potential attacker can then try to steal it. Async reset is generally
discouraged in an FPGA, since it's very often a highway to failed timing, but
we use it knowingly. Now another catch is that our convention is to use
active-low reset signal polarity, since we might go for an ASIC in the future
and that's what you would use there. The problem is that currently we use an
FPGA, where most of the primitives have active-high reset ports. ISE will
throw in an invertor LUT during synthesis and then route all the reset signals
from this LUT. What you get is a "root" invertor LUT, that effectively resets
an entire design. No wonder global placement takes hours. Moreover, this extra
LUT doesn't allow easy replication of the reset signal. This special replicator
module manually instantiates as many invertor LUTs as necessary inside of a
generate loop. Luckily, manually instantiated CLB primitives aren't optimized
away during synthesis (thanks, Xilinx, seriously). Those invertor LUTs are then
followed by asynchronous active-low localized reset generators, that also can't
be optimized away.
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The core selector is now multi-cycle (see /core/platform/alpha commit
35359243a63cac4a9e8cce6bd718f17756ce8a98 message for more details). In short,
for write operations, every core now has its own copy of chip select, address
and write data registers. For read operations we should never ever need the
combinational readback multiplexor again, it just won't meet timing with so
many complex cores. Cores with combinational outputs, primarily those that
don't have block memory inside, always have additional output registers.
Moreover, the readback multiplexor is now registered too, this is required to
get the multicycle constraint to work properly (again, refer to the
aforementioned commit message).
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* new 'modexpng' target builds just the ModExpNG (this is mostly for various
testing purposes)
* new 'hsm_ng' target buils the plain old 'hsm' config + 1x ModExpNG
Also added high-speed clock for the new clock manager.
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* Added modules from core/lib
* Fixed the problem with ECDSA not compiling without ModExp included
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By moving most of the domain-specific knowledge from the script to the
config file, we can a) merge back the fork in platform/alpha, and b) remove
the special-case code that has to know about the modexp and trng cores.
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static core_selector modules.
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static core_selector modules.
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cores)
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Moved default assignments in output select to before the case to make ISE happier. Added proper name of process.
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defines that are internal to the modexp core. Now the modexp core does not get optimized away.
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math core selector module. This module instantiates the modexp core. (3) Minor cleanup of file headers. The core selector is not coretest for example.
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