core/platform/common - Support code used to build projects, not tied to a particular platform

Age	Commit message (Collapse)	Author
2021-07-19	Fixed copyright notices.HEAD master	Pavel V. Shatov (Meister)

2021-06-07	Add sha3 core	Paul Selkirk

2020-09-06	core_config.py didn't really work with Python 3 yet	Rob Austein

2020-04-29	The new keywrap core now talks directly to the mkmif core.	Paul Selkirk

2020-03-25	Move keywrap from user/js to core/util, replace aes core in the hsm project.	Paul Selkirk
	Also re-order cores to make allocation infinitesimally faster for RSA signing.
2020-03-14	Move modexpng from user/shatov to core/math, promote to default modexp for ↵	Paul Selkirk
	Alpha board.
2020-02-26	Merge branch 'js_keywrap' to 'master'	Paul Selkirk

2020-01-23	Added reset replicator module. Details below.	Pavel V. Shatov (Meister)
	Due to security reasons, we must use async reset for sensitive parts of the design. In short, if the system clock is stopped, which is definitely an abnormal situation, sync reset won't let us to wipe secret information and a potential attacker can then try to steal it. Async reset is generally discouraged in an FPGA, since it's very often a highway to failed timing, but we use it knowingly. Now another catch is that our convention is to use active-low reset signal polarity, since we might go for an ASIC in the future and that's what you would use there. The problem is that currently we use an FPGA, where most of the primitives have active-high reset ports. ISE will throw in an invertor LUT during synthesis and then route all the reset signals from this LUT. What you get is a "root" invertor LUT, that effectively resets an entire design. No wonder global placement takes hours. Moreover, this extra LUT doesn't allow easy replication of the reset signal. This special replicator module manually instantiates as many invertor LUTs as necessary inside of a generate loop. Luckily, manually instantiated CLB primitives aren't optimized away during synthesis (thanks, Xilinx, seriously). Those invertor LUTs are then followed by asynchronous active-low localized reset generators, that also can't be optimized away.
2020-01-23	Testbench for the new multicycle core selector.	Pavel V. Shatov (Meister)

2020-01-23	Reworked core selector generation script.	Pavel V. Shatov (Meister)
	The core selector is now multi-cycle (see /core/platform/alpha commit 35359243a63cac4a9e8cce6bd718f17756ce8a98 message for more details). In short, for write operations, every core now has its own copy of chip select, address and write data registers. For read operations we should never ever need the combinational readback multiplexor again, it just won't meet timing with so many complex cores. Cores with combinational outputs, primarily those that don't have block memory inside, always have additional output registers. Moreover, the readback multiplexor is now registered too, this is required to get the multicycle constraint to work properly (again, refer to the aforementioned commit message).
2020-01-23	Added support for ModExpNG core:	Pavel V. Shatov (Meister)
	* new 'modexpng' target builds just the ModExpNG (this is mostly for various testing purposes) * new 'hsm_ng' target buils the plain old 'hsm' config + 1x ModExpNG Also added high-speed clock for the new clock manager.
2019-01-22	Rebase js_keywrap from masterjs_keywrap	Paul Selkirk

2019-01-22	Track Joachim's latest keywrap core - unroll bank-switched memory into a ↵	Paul Selkirk
	number of core register blocks.
2019-01-22	core.cfg [project keywrap]:	Paul Selkirk
	We want two modexp cores for parallel CRT (and we fail badly if we don't get them). Also add ecdsa cores, so we can meaningfully compare results vs stock bitstream.
2019-01-22	Add support for Joachim's keywrap core.	Paul Selkirk

2018-12-20	Merge branch 'master' of git.cryptech.is:core/platform/common	Pavel V. Shatov (Meister)

2018-12-19	* Updated core.cfg to match the changes made to ECDSA cores	Pavel V. Shatov (Meister)
	* Added modules from core/lib * Fixed the problem with ECDSA not compiling without ModExp included
2018-11-13	Catch up with Pavel moving things to core/lib. I suspect more will follow.	Paul Selkirk

2018-09-11	Track Joachim's latest keywrap core - unroll bank-switched memory into a ↵	Paul Selkirk
	number of core register blocks.
2018-08-23	core.cfg [project keywrap]:	Paul Selkirk
	We want two modexp cores for parallel CRT (and we fail badly if we don't get them). Also add ecdsa cores, so we can meaningfully compare results vs stock bitstream.
2018-08-15	Add support for Joachim's keywrap core.	Paul Selkirk

2017-09-13	Add second modexp core for parallel CRT.	Rob Austein

2017-09-09	systolic_crt modexpa7 needs a bigger chunk of address space.	Rob Austein

2017-08-09	reset_n vs rst_n, pax guys.	Rob Austein

2017-08-09	Drop duplicate bram_1rw_1ro_readfirst module.	Rob Austein

2017-08-09	Update modexpa7 filenames.	Rob Austein

2017-08-09	Don't try to synthesize include files.	Rob Austein

2017-08-08	Allow core instantation parameters.	Rob Austein

2017-08-08	Update modexpa7 path names for systolic branch.	Rob Austein

2017-05-12	ECDSA cores no longer "experimental", include them in default build.	Rob Austein

2017-03-07	ECDSA cores.	Rob Austein

2017-03-06	Add ecdsa384 core.	Rob Austein

2017-01-20	Add ecdsa256 core.	Rob Austein

2017-01-19	split [project hsm]	Paul Selkirk

2017-01-17	Rename and rewrite the core_selector generator.	Paul Selkirk
	By moving most of the domain-specific knowledge from the script to the config file, we can a) merge back the fork in platform/alpha, and b) remove the special-case code that has to know about the modexp and trng cores.
2016-05-17	add the new mkmif core	Paul Selkirk

2015-12-13	whack copyrights	Paul Selkirk

2015-11-18	drat, pushed too soon	Paul Selkirk

2015-11-18	Move core_selector config script here from core/platform/novena, remove ↵	Paul Selkirk
	static core_selector modules.
2015-11-18	Move core_selector config script here from core/platform/novena, remove ↵	Paul Selkirk
	static core_selector modules.
2015-11-12	Merge branch 'modexps6'	Paul Selkirk

2015-11-12	Change reset to active-low.	Paul Selkirk

2015-07-17	experimental modexps6 (which requires changing the read timing on all other ↵	Paul Selkirk
	cores)
2015-05-08	Fixed missing assignment to debug port if the RNGS segment is not enabled. ↵	Joachim Strömbergson
	Moved default assignments in output select to before the case to make ISE happier. Added proper name of process.
2015-05-08	Fixed incorrect bitwidth of address to modexp core. Removed address block ↵	Joachim Strömbergson
	defines that are internal to the modexp core. Now the modexp core does not get optimized away.
2015-05-05	Populate cipher_selector; finesse math_selector.	Paul Selkirk

2015-05-04	Adding a core license file.	Joachim Strömbergson

2015-05-04	Adding math segment in core selector.	Joachim Strömbergson

2015-04-29	Cleanup: add error port, conditionalize segments.	Paul Selkirk

2015-04-27	(1) Added segment for math cores in the core selector. (2) Added specific ↵	Joachim Strömbergson
	math core selector module. This module instantiates the modexp core. (3) Minor cleanup of file headers. The core selector is not coretest for example.