diff options
| -rw-r--r-- | config/core.cfg | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/config/core.cfg b/config/core.cfg index 222a8e0..adce434 100644 --- a/config/core.cfg +++ b/config/core.cfg @@ -90,12 +90,16 @@ cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384 # super-size it cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes aes aes modexp modexp modexp ecdsa256 ecdsa256 ecdsa256 ecdsa384 ecdsa384 ecdsa384 +[project keywrap] +# for testing Joachim's keywrap core with RSA signing +cores = mkmif sha256 aes trng modexp keywrap + # [core] sections # # vfiles: A list of Verilog files to include in the vfiles list when -# including a particular core. All (optional) cores must have a -# vfiles option, so that the configuration program knows what to put -# into core_vfiles.mk. +# including a particular core. File paths are relative to the cores/ +# directory. All (optional) cores must have a vfiles option, so that the +# configuration program knows what to put into core_vfiles.mk. # # requires: A list of other cores whose vfiles must be loaded to build # this core. This has no effect on the generated core_selector.v @@ -214,6 +218,7 @@ vfiles = math/modexpa7/src/rtl/pe/modexpa7_subtractor32.v math/modexpa7/src/rtl/pe/modexpa7_systolic_pe.v math/modexpa7/src/rtl/util/bram_1rw_readfirst.v + math/ecdsalib/rtl/util/bram_1rw_1ro_readfirst.v [core modexps6] # ModExp for Xilinx Spartan-6 @@ -374,3 +379,14 @@ vfiles = math/ecdsalib/rtl/multiword/mw_comparator.v math/ecdsalib/rtl/multiword/mw_mover.v math/ecdsalib/rtl/util/bram_1rw_1ro_readfirst.v + +[core keywrap] +# Joachim's experimental AES-keywrap core +requires = aes +block memory = yes +error wire = yes +module name = keywrap +vfiles = + ../user/js/keywrap/src/rtl/keywrap.v + ../user/js/keywrap/src/rtl/keywrap_core.v + ../user/js/keywrap/src/rtl/keywrap_mem.v |