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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-12-20 13:36:11 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-12-20 13:36:11 +0300
commit5ae9fac48b80c3f27d9f78e3be89cf1d1d59a707 (patch)
tree030688f3cca38d56a48daa63d3329f74f0a4d041 /config
parentad19a5b3fdaca8b9b8c792790151e40e8e6d4991 (diff)
parent13575db793ca8531d2e67b72462b2898a5676171 (diff)
Merge branch 'master' of git.cryptech.is:core/platform/common
Diffstat (limited to 'config')
-rw-r--r--config/core.cfg4
1 files changed, 0 insertions, 4 deletions
diff --git a/config/core.cfg b/config/core.cfg
index 254b61a..d6de1fa 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -86,10 +86,6 @@ cores = sha256 aes trng modexp
# Make me one with everything, except we want two modexp cores for parallel CRT
cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384
-[project hsm-super]
-# super-size it
-cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes aes aes modexp modexp modexp ecdsa256 ecdsa256 ecdsa256 ecdsa384 ecdsa384 ecdsa384
-
# [core] sections
#
# vfiles: A list of Verilog files to include in the vfiles list when