Move modexpng from user/shatov to core/math, promote to default modexp for Alpha board.

1 files changed, 37 insertions, 53 deletions

diff --git a/config/core.cfg b/config/core.cfg
index 697f8bc..65985ca 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -32,7 +32,7 @@ project = hsm
 # Cryptech Alpha board
 bus name = fmc
 bus width = 24
-modexp = modexpa7
+modexp = modexpng
 extra wires =
    output wire         mkm_sclk,
    output wire         mkm_cs_n,
@@ -70,34 +70,18 @@ cores = sha1 sha256 sha512
 # for testing just the True Random Number Generator
 cores = trng
 
-[project modexp]
-# for testing just the Modular Exponentiation
-cores = modexp
-
-[project modexpng]
-# for testing just the ModExpNG
-cores = modexpng
-
-[project mkmif]
-# for testing just the Master Key Memory Interface
-cores = mkmif
-
 [project rsa]
 # RSA signing and verification. This is as much as will fit on the
 # Novena's Spartan-6 FPGA.
 cores = sha256 aes trng modexp mkmif
 
 [project hsm]
-# Make me one with everything, except we want two modexp cores for parallel CRT
-cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384
+# Make me one with everything, except we want a lot of modexp for RSA signing
+cores = sha1 sha256 sha512 mkmif aes trng modexp modexp modexp modexp ecdsa256 ecdsa384
 
-[project hsm_ng]
-# Make me one with everything, except we want the new ModExpNG core
-cores = sha1 sha256 sha512 aes trng modexp modexp modexpng mkmif ecdsa256 ecdsa384
-
-[project hsm_ng_keywrap]
-# everything, with the full range of modexp and keywrap options
-cores = sha1 sha256 sha512 aes keywrap trng modexp modexp modexpng mkmif ecdsa256 ecdsa384
+[project hsm-keywrap]
+# Make me one with everything, except we want a lot of modexp for RSA signing
+cores = sha1 sha256 sha512 mkmif keywrap trng modexp modexp modexp ecdsa256 ecdsa384
 
 # [core] sections
 #
@@ -195,6 +179,37 @@ vfiles =
 	cipher/chacha/src/rtl/chacha_core.v
 	cipher/chacha/src/rtl/chacha_qr.v
 
+[core modexpng]
+# next-gen ModExp for Xilinx Artix-7
+core blocks = 16
+block memory = yes
+error wire = no
+module name = modexpng_wrapper
+reset name = rst_n
+extra ports =
+      .clk_core(core_clk),
+vfiles =
+	math/modexpng/rtl/modexpng_wrapper.v
+	math/modexpng/rtl/modexpng_core_top.v
+	math/modexpng/rtl/modexpng_general_worker.v
+	math/modexpng/rtl/modexpng_mmm_dual.v
+	math/modexpng/rtl/modexpng_reductor.v
+	math/modexpng/rtl/modexpng_dsp_array_block.v
+	math/modexpng/rtl/modexpng_io_block.v
+	math/modexpng/rtl/modexpng_io_manager.v
+	math/modexpng/rtl/modexpng_storage_block.v
+	math/modexpng/rtl/modexpng_storage_manager.v
+	math/modexpng/rtl/modexpng_uop_rom.v
+	math/modexpng/rtl/modexpng_uop_engine.v
+	math/modexpng/rtl/modexpng_recombinator_block.v
+	math/modexpng/rtl/modexpng_recombinator_cell.v
+	math/modexpng/rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v
+	math/modexpng/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
+	math/modexpng/rtl/modexpng_sdp_36k_x18_wrapper_xilinx.v
+	math/modexpng/rtl/modexpng_sdp_36k_x16_x32_wrapper_xilinx.v
+	math/modexpng/rtl/modexpng_sdp_36k_x32_x16_wrapper_xilinx.v
+	math/modexpng/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v
+
 [core modexpa7]
 # ModExp for Xilinx Artix-7
 core blocks = 8
@@ -224,37 +239,6 @@ vfiles =
 	lib/lowlevel/artix7/dsp48e1_wrapper.v
 	lib/lowlevel/artix7/dsp48e1_wrapper_modexp.v
 
-[core modexpng]
-# ModExpNG for Xilinx Artix-7
-core blocks = 16
-block memory = yes
-error wire = no
-module name = modexpng_wrapper
-reset name = rst_n
-extra ports =
-      .clk_core(core_clk),
-vfiles =
-	../user/shatov/modexpng/rtl/modexpng_wrapper.v
-	../user/shatov/modexpng/rtl/modexpng_core_top.v
-	../user/shatov/modexpng/rtl/modexpng_general_worker.v
-	../user/shatov/modexpng/rtl/modexpng_mmm_dual.v
-	../user/shatov/modexpng/rtl/modexpng_reductor.v
-	../user/shatov/modexpng/rtl/modexpng_dsp_array_block.v
-	../user/shatov/modexpng/rtl/modexpng_io_block.v
-	../user/shatov/modexpng/rtl/modexpng_io_manager.v
-	../user/shatov/modexpng/rtl/modexpng_storage_block.v
-	../user/shatov/modexpng/rtl/modexpng_storage_manager.v
-	../user/shatov/modexpng/rtl/modexpng_uop_rom.v
-	../user/shatov/modexpng/rtl/modexpng_uop_engine.v
-	../user/shatov/modexpng/rtl/modexpng_recombinator_block.v
-	../user/shatov/modexpng/rtl/modexpng_recombinator_cell.v
-	../user/shatov/modexpng/rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v
-	../user/shatov/modexpng/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
-	../user/shatov/modexpng/rtl/modexpng_sdp_36k_x18_wrapper_xilinx.v
-	../user/shatov/modexpng/rtl/modexpng_sdp_36k_x16_x32_wrapper_xilinx.v
-	../user/shatov/modexpng/rtl/modexpng_sdp_36k_x32_x16_wrapper_xilinx.v
-	../user/shatov/modexpng/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v
-
 [core modexps6]
 # ModExp for Xilinx Spartan-6
 core blocks = 4