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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-01-23 13:08:59 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-01-23 13:22:13 +0300
commit5807b0bfd7efe8dd3f83d679730241847517980b (patch)
treed57844e74edb8cec0ac967497085201a0f9f4773 /bench
parent4f5c4453343430cce0067007deace5c1ddd7c29e (diff)
Reworked core selector generation script.
The core selector is now multi-cycle (see /core/platform/alpha commit 35359243a63cac4a9e8cce6bd718f17756ce8a98 message for more details). In short, for write operations, every core now has its own copy of chip select, address and write data registers. For read operations we should never ever need the combinational readback multiplexor again, it just won't meet timing with so many complex cores. Cores with combinational outputs, primarily those that don't have block memory inside, always have additional output registers. Moreover, the readback multiplexor is now registered too, this is required to get the multicycle constraint to work properly (again, refer to the aforementioned commit message).
Diffstat (limited to 'bench')
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