Merge branch 'js_keywrap' to 'master'

2 files changed, 21 insertions, 5 deletions

diff --git a/config/core.cfg b/config/core.cfg
index 6efc4af..697f8bc 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -85,7 +85,7 @@ cores = mkmif
 [project rsa]
 # RSA signing and verification. This is as much as will fit on the
 # Novena's Spartan-6 FPGA.
-cores = sha256 aes trng modexp
+cores = sha256 aes trng modexp mkmif
 
 [project hsm]
 # Make me one with everything, except we want two modexp cores for parallel CRT
@@ -95,12 +95,16 @@ cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384
 # Make me one with everything, except we want the new ModExpNG core
 cores = sha1 sha256 sha512 aes trng modexp modexp modexpng mkmif ecdsa256 ecdsa384
 
+[project hsm_ng_keywrap]
+# everything, with the full range of modexp and keywrap options
+cores = sha1 sha256 sha512 aes keywrap trng modexp modexp modexpng mkmif ecdsa256 ecdsa384
+
 # [core] sections
 #
 # vfiles: A list of Verilog files to include in the vfiles list when
-#   including a particular core.  All (optional) cores must have a
-#   vfiles option, so that the configuration program knows what to put
-#   into core_vfiles.mk.
+#   including a particular core. File paths are relative to the cores/
+#   directory. All (optional) cores must have a vfiles option, so that the
+#   configuration program knows what to put into core_vfiles.mk.
 #
 # requires: A list of other cores whose vfiles must be loaded to build
 #   this core.  This has no effect on the generated core_selector.v
@@ -365,3 +369,15 @@ vfiles =
 	lib/modular/modular_adder.v
 	lib/modular/modular_subtractor.v
 	lib/lowlevel/artix7/dsp48e1_wrapper.v
+
+[core keywrap]
+# Joachim's experimental AES-keywrap core
+requires = aes
+core blocks = 32
+block memory = yes
+error wire = yes
+module name = keywrap
+vfiles =
+	../user/js/keywrap/src/rtl/keywrap.v
+	../user/js/keywrap/src/rtl/keywrap_core.v
+	../user/js/keywrap/src/rtl/keywrap_mem.v
diff --git a/config/core_config.py b/config/core_config.py
index 61e77d5..d511228 100755
--- a/config/core_config.py
+++ b/config/core_config.py
@@ -234,7 +234,7 @@ class Core(object):
         self.block_max = self.blocks - 1
         if self.blocks > 1:
             try:
-                self.block_bits = {4:2, 8:3, 16:4}[self.blocks]
+                self.block_bits = {4:2, 8:3, 16:4, 32:5}[self.blocks]
             except KeyError:
                 raise ValueError, "In [{}]: unexpected value \"core blocks = {}\"".format(self.cfg_section, self.blocks)
             self.block_bit_max = self.block_bits - 1